公开(公告)号：US5495569A

公开(公告)日：1996-02-27

申请号：US366778

申请日：1994-12-30

Applicant: Gary B. Kotzur

Inventor： Gary B. Kotzur

IPC: G06F11/00 ,  G06F11/20 ,  G06F11/22

CPC classification number: G06F11/0757 ,  G06F11/0724 ,  G06F11/20 ,  G06F11/22

Abstract: A hot spare boot circuit that automatically switches from a non-operational CPU to an operational CPU for powering up the computer system. In the multiprocessor computer system, a first CPU is designated to perform power on operations. If the first CPU fails, which is determined when a dead man counter in the hot spare boot circuit times out, the hot spare circuit ensures that the first CPU is in a disabled state. Next, the hot spare boot circuit identifies an operational second CPU, reinitializing certain ID information as necessary such that the second CPU can properly perform power on operations. The hot spare boot then awakens the second CPU, using a startup interprocessor interrupt in one embodiment, or simply negating the hard reset of the second CPU in a second embodiment. The second CPU then proceeds to perform the power on functions.

Abstract translation: 一个热备用引导电路，可自动从非操作CPU切换到运行CPU，以便为计算机系统供电。 在多处理器计算机系统中，指定第一CPU执行上电操作。 如果第一个CPU出现故障，当热备用引导电路中的死亡计数器超时时确定，热备用电路确保第一个CPU处于禁用状态。 接下来，热备用引导电路识别操作的第二CPU，根据需要重新初始化某些ID信息，使得第二CPU可以正常地执行上电操作。 热备用引导然后在一个实施例中唤醒第二CPU，使用启动处理器中断，或者在第二实施例中简单地否定第二CPU的硬复位。 然后第二个CPU继续执行上电功能。

公开(公告)号：US5481730A

公开(公告)日：1996-01-02

申请号：US825399

申请日：1992-01-24

Applicant: Alan E. Brown ,  David S. Lin

Inventor： Alan E. Brown ,  David S. Lin

IPC: G06F1/26 ,  G06F1/00 ,  G06F1/02

CPC classification number: G06F1/26 ,  Y10T307/549 ,  Y10T307/625

Abstract: A power supply monitoring and control circuit using a microcontroller to remotely monitor and control the functions and conditions of a power supply. The power supply monitoring and control circuit is coupled to the primary and secondary sides of a power supply to monitor important voltage and current signals of the power supply, such as the output voltages and currents, and to control the various parameters of the power supply such as the output voltage and current limits. Analog to digital interface circuitry is provided to convert the power supply voltage and current signals to digital signals which are retrieved by a microcontroller which converts the digital signals to numbers representing the values of the power supply signals, and then stores the numbers. The microcontroller is also interfaced to reference and feedback signals of the power supply to control the power supply's operation. The microcontroller further keeps track of the total elapsed time of operation and the total number of times the power supply has been powered up. The power supply monitoring and control circuit operates as a slave to a host computer system so that a system operator can retrieve all of the monitored information and can control the operation of power supply. The host computer system communicates with the power supply monitoring and control circuit through a serial link, so that the host computer can be remotely located. The present invention also provides self-calibration to assure accurate data.

Abstract translation: 电源监控电路采用微控制器远程监控和控制电源的功能和状况。 电源监视和控制电路耦合到电源的一侧和二侧，以监测电源的重要电压和电流信号，例如输出电压和电流，并且控制电源的各种参数，例如 作为输出电压和电流限制。 提供模拟数字接口电路以将电源电压和电流信号转换成由微控制器检索的数字信号，微控制器将数字信号转换成表示电源信号值的数字，然后存储数字。 微控制器还连接到电源的参考和反馈信号以控制电源的操作。 微控制器进一步跟踪操作的总经过时间和电源已经通电的总次数。 电源监视和控制电路作为主计算机系统的从设备操作，以便系统操作员可以检索所有被监视的信息并且可以控制电源的操作。 主计算机系统通过串行链路与电源监控电路进行通信，使得主机可以远程定位。 本发明还提供自校准以确保准确的数据。

公开(公告)号：US5475829A

公开(公告)日：1995-12-12

申请号：US34525

申请日：1993-03-22

Applicant: Gary W. Thome

Inventor： Gary W. Thome

IPC: G06F9/38 ,  G06F1/32 ,  G06F12/14 ,  G06F13/16

CPC classification number: G06F13/1615 ,  G06F12/1491

Abstract: A memory controller which makes maximum use of any processor pipelining and runs a large number of cycles concurrently. The memory controller can utilize different speed memory devices at their desired optimal speeds. The functions are performed by a plurality of simple, interdependent state machines, each responsible for one small portion of the overall operation. As each state machine reaches has completed its function, it notifies a related state machine that it can now proceed and proceeds to wait for its next start or proceed indication. The next state machine operates in a similar fashion. The state machines responsible for the earlier portions of a cycle have started their tasks on the next cycle before the state machines responsible for the later portions of the cycle have completed their tasks. The memory controller is logically organized as three main blocks, a front end block, a memory block and a host block, each being responsible for interactions with its related bus and components and interacting with the various other blocks for handshaking. The memory controller operates in system management mode to override any write protect status of memory so that the SMRAM can be located in the main memory space and be write protected during normal operations but be full usable during system management mode.

Abstract translation: 一个内存控制器，最大程度地利用任何处理器流水线并同时运行大量的周期。 存储器控制器可以以其期望的最佳速度利用不同的速度存储器件。 这些功能由多个简单的相互依赖的状态机执行，每个状态机负责整个操作的一小部分。 当每个状态机达到完成其功能时，它通知相关状态机现在可以继续，并继续等待下一个启动或继续指示。 下一台状态机以类似的方式运行。 负责循环早期部分的状态机在下一个循环中开始执行任务，然后负责循环后期部分的状态机完成任务。 存储器控制器在逻辑上组织为三个主要块，前端块，存储器块和主机块，每个都负责与其相关总线和组件的交互，并与各种其他块进行交互。 存储器控制器以系统管理模式操作以覆盖存储器的任何写保护状态，使得SMRAM可以位于主存储器空间中，并且在正常操作期间被写保护，但是在系统管理模式期间可以完全可用。

公开(公告)号：US5469554A

公开(公告)日：1995-11-21

申请号：US259636

申请日：1994-06-14

Applicant: Brian B. Tucker ,  Brian V. Belmont

Inventor： Brian B. Tucker ,  Brian V. Belmont

IPC: G06F11/267 ,  G06F12/06 ,  G06F13/40 ,  G06F11/20

CPC classification number: G06F11/221 ,  G06F12/0684 ,  G06F13/4086

Abstract: A computer system determines the presence of a device on the system bus that responds to I/O or memory reads by performing an I/O or memory read with data bus pulled to its normally undriven state. If the value returned is other than the data bus' normally undriven value, it is determined that a device is responsive to that I/O or memory read. Otherwise, the system then pulls the data bus to other than its normally undriven state and performs another I/O or memory read. If the value returned is again the value of the data bus' normally undriven state, it is determined that a device is present because it is driving the data bus back to its normally undriven state. Otherwise, it is determined that a device is not driving the data bus in response to an I/O or memory read. Further, the computer system according to the invention makes the determination of whether a device is driving the bus using a comparator to compare the level present on the data bus in response to the I/O or memory reads.

Abstract translation: 计算机系统通过执行I / O或存储器读取，确定系统总线上存在的设备对I / O或存储器读取做出响应，数据总线被拉至其正常未驱动状态。 如果返回的值不是数据总线'通常未驱动的值，则确定设备响应于该I / O或存储器读取。 否则，系统然后将数据总线拉至除其正常未驱动状态以外的其他I / O或存储器读取。 如果返回的值再次是数据总线'正常未驱动状态的值，则确定设备存在，因为它正在将数据总线恢复到其正常未驱动状态。 否则，确定设备不是响应于I / O或存储器读取来驱动数据总线。 此外，根据本发明的计算机系统使用比较器确定设备是否正在驱动总线，以便响应于I / O或存储器读取来比较数据总线上存在的电平。

公开(公告)号：US5459652A

公开(公告)日：1995-10-17

申请号：US188108

申请日：1994-01-28

Applicant: Richard A. Faulk

Inventor： Richard A. Faulk

IPC: H02M1/00 ,  H02M1/36 ,  H02M3/335

CPC classification number: H02M1/36 ,  Y10S323/901

Abstract: A boot strap control circuit including a depletion mode NMOS transistor to effectively switch a boot strap bleed resistor out of the circuit after power up is achieved. The NMOS transistor is initially turned fully on to allow current to flow through the bleed resistor to a pulse width modulation circuit (PWM) upon power up and to allow early control by the PWM. When the PWM reaches operating power, it asserts its reference voltage output high, activating a transistor switch to turn the NMOS transistor fully off. A capacitor maintains power to the PWM until an auxiliary winding of the power transformer develops sufficient voltage to operate the PWM. In the event of failure of the auxiliary winding, the NMOS transistor operates discretely, turning on and off at a low duty cycle, rather than operating in the linear mode. In this manner, the NMOS transistor and bleed resistor assure low power during normal operation and safe operation at all times.

Abstract translation: 包括耗尽型NMOS晶体管的引导带控制电路能够在上电之后有效地将引导带放电电阻器切换出电路。 NMOS晶体管最初完全导通，以允许电流在上电时通过放电电阻器流过脉宽调制电路（PWM），并允许PWM的早期控制。 当PWM达到工作电源时，它将其参考电压输出置为高电平，激活晶体管开关，使NMOS晶体管完全关断。 电容器维持PWM的电源，直到电源变压器的辅助绕组产生足够的电压来操作PWM。 在辅助绕组失效的情况下，NMOS晶体管以离散方式工作，在低占空比下导通和关断，而不是在线性模式下工作。 以这种方式，NMOS晶体管和放电电阻在正常工作期间保证低功耗，并始终保证安全运行。

公开(公告)号：US5454081A

公开(公告)日：1995-09-26

申请号：US937475

申请日：1992-08-28

Applicant: Gary W. Thome

Inventor： Gary W. Thome

IPC: G06F13/40 ,  G06F11/30 ,  G06F13/20 ,  G06F13/42

CPC classification number: G06F13/4068

Abstract: A circuit that automatically detects whether an input/output expansion board is connected to an EISA system or an ISA system. The circuit monitors the expansion bus for EISA slot-specific I/O cycles by sampling the bus signals AENx and BALE when either of the IORC, or IOWC, signals are asserted. When the circuit detects an EISA slot-specific I/O operation on the expansion bus, a signal is generated indicating that the expansion bus is the EISA bus. This determination allows an ISA expansion board to take advantage of certain EISA features when it is connected to an EISA system. Using a circuit to determine expansion bus type removes the need for a jumper to provide the same function, thus providing greater ease of use.

Abstract translation: 自动检测输入/输出扩展板是否连接到EISA系统或ISA系统的电路。 当任何IORC或IOWC信号被断言时，电路通过对总线信号AENx和BALE进行采样来监视EISA槽专用I / O周期的扩展总线。 当电路在扩展总线上检测到EISA槽专用I / O操作时，产生一个指示扩展总线是EISA总线的信号。 该确定允许ISA扩展板在连接到EISA系统时利用某些EISA功能。 使用电路来确定扩展总线类型不需要跳线来提供相同的功能，从而提供更大的易用性。

公开(公告)号：US5336985A

公开(公告)日：1994-08-09

申请号：US973267

申请日：1992-11-09

Applicant: Philip J. McKenzie

Inventor： Philip J. McKenzie

IPC: G05F1/56

CPC classification number: G05F1/56 ,  Y10T307/43

Abstract: A tapped inductor slave regulating circuit provides a second slave output voltage derived from a tapped connection to the filter storage inductor of a first output voltage of a switching power supply converter. In the converter, an unregulated voltage is provided through a switching circuit to a storage inductor to develop a first output. The switching circuit is turned off and a synchronous rectifier is turned on to freewheel the current through the storage inductor and the load. The storage inductor is center-tapped and coupled to a switching circuit to provide a second slaved output. The location of the center tap is chosen to provide the proper voltage of the second output. In one embodiment, the switching circuit for the slaved output is turned on during the freewheel portion of each cycle to provide a proper voltage level for the second output. In another embodiment, a separate local feedback circuit is provided to further regulate the second output voltage level.

Abstract translation: 抽头电感器从调节电路提供从与开关电源转换器的第一输出电压的滤波器存储电感器的抽头连接导出的第二从输出电压。 在转换器中，通过开关电路向存储电感器提供未调节的电压以产生第一输出。 开关电路被关闭，并且同步整流器导通以使通过存储电感器和负载的电流释放。 存储电感器被中心抽头并耦合到开关电路以提供第二从属输出。 选择中心抽头的位置以提供第二输出的适当电压。 在一个实施例中，用于从动输出的开关电路在每个周期的续流部分期间导通，以为第二输出提供适当的电压电平。 在另一个实施例中，提供了单独的局部反馈电路以进一步调节第二输出电压电平。

公开(公告)号：US5333293A

公开(公告)日：1994-07-26

申请号：US757701

申请日：1991-09-11

Applicant: Randy M. Bonella

Inventor： Randy M. Bonella

IPC: G06F15/16 ,  G06F9/305

CPC classification number: G06F15/16

Abstract: A synchronous memory controller capable of operating with three different frequency microprocessors and yet providing similar DRAM timings. Input frequencies of 32, 25 and 33 MHz correspond to 16, 25 and 33 MHz microprocessors. Various states are bypassed at certain frequencies to allow the various memory, latch and buffer control signals to be produced uniformly. The memory controller also handles operations from external buses, such as the EISA and ISA buses at the various input frequencies. These external bus cycles are controlled by separate state machines, which also have states bypassed for certain input frequencies.

Abstract translation: 同步存储器控制器，能够与三个不同的频率微处理器一起工作，并提供类似的DRAM时序。 32,25和33 MHz的输入频率对应于16,25和33 MHz微处理器。 各种状态在某些频率旁路，以允许均匀地产生各种存储器，锁存器和缓冲器控制信号。 存储器控制器还处理来自外部总线的操作，例如在各种输入频率下的EISA和ISA总线。 这些外部总线周期由单独的状态机控制，这些状态机也具有绕过某些输入频率的状态。

公开(公告)号：US5303364A

公开(公告)日：1994-04-12

申请号：US999677

申请日：1992-12-30

Applicant: Dale J. Mayer ,  Paul R. Culley ,  Mark Taylor

Inventor： Dale J. Mayer ,  Paul R. Culley ,  Mark Taylor

IPC: G06F12/02 ,  G06F12/08 ,  G06F12/00 ,  G06F13/00

CPC classification number: G06F12/0882 ,  G06F12/0215

Abstract: A computer system has a processor coupled to a cache controller, uses page mode memory devices and performs page hit detection on the processor local bus. Column address and data values are latched by a memory controller on memory write operations to allow early completion of the cycle so that the next cycle can partially overlap. This allows the use of economical memories and yet have zero wait state page hit operation.

Abstract translation: 计算机系统具有耦合到高速缓存控制器的处理器，使用页面模式存储器件并在处理器局部总线上执行页面命中检测。 列地址和数据值由存储器控制器在存储器写入操作中锁存以允许早期完成循环，使得下一个周期可以部分重叠。 这允许使用经济的记忆，而且具有零等待状态页命中操作。

公开(公告)号：US5289584A

公开(公告)日：1994-02-22

申请号：US719198

申请日：1991-06-21

Applicant: Gary W. Thome ,  Mustafa A. Hamid

Inventor： Gary W. Thome ,  Mustafa A. Hamid

IPC: G06F12/08 ,  G06F13/16 ,  G06F13/00

CPC classification number: G06F13/1673 ,  G06F12/0879

Abstract: At least two double buffers or FIFOs, each FIFO including a first group of latches in series with a second group of latches, coupled between a host data bus and a corresponding bank or way of interleaved memory. The inputs of the first group of latches are coupled to the host data bus, and the inputs of the second group of latches are coupled to the outputs of the first group of latches of each double buffer or FIFO. The outputs of the second group of latches are coupled to the memory data bus of the corresponding way of interleaved memory. During a burst write sequence, an address is placed on the host address bus and a series of data doublewords are sequentially placed onto the host data bus, while the DRAMs of main memory are entering into page mode. The first group of latches of each double buffer or FIFO latches in every other data doubleword. The second level of latches stores the data from the corresponding first level of latches to provide the data to the DRAMs according to the timing requirements of the DRAMs. In this manner, the CPU or cache controller providing data to the host bus may operate at full speed without inserting wait states while the DRAMs enter into page mode.

Abstract translation: 至少两个双缓冲器或FIFO，每个FIFO包括与第二组锁存器串联的第一组锁存器，耦合在主机数据总线和对应的存储体或交织存储器的方式之间。 第一锁存器组的输入耦合到主机数据总线，第二组锁存器的输入耦合到每个双缓冲器或FIFO的第一锁存器组的输出端。 第二组锁存器的输出被耦合到存储器数据总线上，该存储器数据总线与相应的交错存储器的方式相连。 在突发写入序列期间，将地址放置在主机地址总线上，并且一系列数据双字依次放置在主机数据总线上，而主存储器的DRAM进入页模式。 每个双缓冲区或FIFO的第一组锁存器锁存在每隔一个数据双字。 第二级锁存器存储来自对应的第一级锁存器的数据，以根据DRAM的定时要求向DRAM提供数据。 以这种方式，向主机总线提供数据的CPU或高速缓存控制器可以全速工作，而不会在DRAM进入寻呼模式时插入等待状态。