公开(公告)号：US07304500B2

公开(公告)日：2007-12-04

申请号：US10748963

申请日：2003-12-29

Applicant: Tzu-Shern Chen ,  Chun-Hsien Lin ,  Ming-Chief Chaw

Inventor： Tzu-Shern Chen ,  Chun-Hsien Lin ,  Ming-Chief Chaw

IPC: H01L25/00 ,  H03K19/177 ,  G06F17/50

CPC classification number: G06F17/5054 ,  H05K1/141 ,  H05K2201/10159 ,  H05K2201/10212 ,  H05K2201/10325 ,  H05K2201/10689

Abstract: A programmable logic module. In the programmable logic module, a first printed circuit board has a socket and a downloading unit. A field programmable gate array (FPGA) is disposed on the first printed circuit board. A nonvolatile memory stores program codes for programming the field programmable gate array. The nonvolatile memory is soldered to a second printed circuit board with a plurality of pins corresponding to the socket, and the second printed circuit board is plugged into the socket of the first printed circuit board. The nonvolatile memory downloads program codes thereof to the field programmable gate array by the downloading unit.

Abstract translation: 可编程逻辑模块。 在可编程逻辑模块中，第一印刷电路板具有插座和下载单元。 现场可编程门阵列（FPGA）设置在第一印刷电路板上。 非易失性存储器存储用于编程现场可编程门阵列的程序代码。 非易失性存储器被焊接到具有与插座对应的多个引脚的第二印刷电路板，并且第二印刷电路板插入第一印刷电路板的插座中。 非易失性存储器通过下载单元将其程序代码下载到现场可编程门阵列。

公开(公告)号：US20070258524A1

公开(公告)日：2007-11-08

申请号：US11381137

申请日：2006-05-02

Applicant: You-Duan Chen

Inventor： You-Duan Chen

IPC: H04L27/28

CPC classification number: H04L27/2662 ,  H04L27/266 ,  H04L2027/0067

Abstract: The invention relates to a phase offset tracking module and method for tracking a phase offset, and in particular, to a phase offset tracking module and method for tracking a phase offset in a receiver. A phase offset tracking method comprises: utilizing a first and a second registers to respectively store a first and a second register values; estimating an error phase according to an input phase and an output phase; setting the first register value to an unit phase error initially; setting the second register value according to the first register value; filtering the error phase to generate a filtered signal according to the first register value; accumulating the filtered signal continuously according to the second register value to generate the output phase; and compensating the phase offset in each input symbol according to the output phase.

Abstract translation: 本发明涉及一种用于跟踪相位偏移的相位偏移跟踪模块和方法，特别涉及用于跟踪接收机中的相位偏移的相位偏移跟踪模块和方法。 相位偏移跟踪方法包括：利用第一和第二寄存器分别存储第一和第二寄存器值; 根据输入相位和输出相位估计误差相位; 最初将第一个寄存器值设置为单位相位误差; 根据第一寄存器值设置第二寄存器值; 过滤误差相位以根据第一寄存器值产生滤波信号; 根据第二寄存器值连续地累积经滤波的信号以产生输出相位; 并且根据输出相位补偿每个输入符号中的相位偏移。

公开(公告)号：US07287245B2

公开(公告)日：2007-10-23

申请号：US10605231

申请日：2003-09-17

Applicant: Yu-Min Wang

Inventor： Yu-Min Wang

IPC: G06F9/44

CPC classification number: G06F11/3636

Abstract: A method for real-time instruction information tracing for recording the information about a plurality of specific instructions executed by a processor. The method contains the following steps. A trace count value is set to an initial value. A trigger count value is set according to the tracing start point. The trace count value is increased whenever a specific instruction executed by the processor. If the increased trace count value is equal to or larger than the trigger count value, record the instruction information about the specific instruction executed by the processor in a buffer; if the buffer is full, stop running the program and output the instruction information stored in the buffer. During this time reset the trigger count value according to the trace count value, reset the trace count value as the initial value, and then start running the program with the processor again.

Abstract translation: 一种用于记录关于由处理器执行的多个特定指令的信息的实时指令信息跟踪的方法。 该方法包含以下步骤。 跟踪计数值设置为初始值。 根据跟踪开始点设置触发计数值。 只要处理器执行的特定指令，跟踪计数值就会增加。 如果增加的跟踪计数值等于或大于触发计数值，则将处理器执行的特定指令的指令信息记录在缓冲器中; 如果缓冲区已满，请停止运行程序并输出缓冲区中存储的指令信息。 在此期间，根据跟踪计数值重置触发计数值，将跟踪计数值重置为初始值，然后再次使用处理器开始运行程序。

公开(公告)号：US07282902B2

公开(公告)日：2007-10-16

申请号：US10708489

申请日：2004-03-07

Applicant: Yuan-Hsun Chang ,  Jia-Jio Huang ,  Cheng-Chung Chou

Inventor： Yuan-Hsun Chang ,  Jia-Jio Huang ,  Cheng-Chung Chou

IPC: G05F3/16

CPC classification number: G05F1/56

Abstract: A voltage regulator apparatus, wherein two transistors are coupled to an output terminal of a voltage regulator, so as to improve the transient response of output voltage and increase the stability of the output voltage. Besides, it avoids the use of an external capacitor.

Abstract translation: 一种电压调节器装置，其中两个晶体管耦合到电压调节器的输出端子，以便改善输出电压的瞬态响应并增加输出电压的稳定性。 此外，它避免了使用外部电容器。

公开(公告)号：US07187163B2

公开(公告)日：2007-03-06

申请号：US10905735

申请日：2005-01-19

Applicant: Shyh-An Chi ,  Wang-Chin Chen

Inventor： Shyh-An Chi ,  Wang-Chin Chen

IPC: G01R31/28 ,  G01R31/26

CPC classification number: G01R31/31712

Abstract: A parametric measuring circuit for minimizing an oscillation effect is provided. The parametric measuring circuit comprises an input detection circuit, an oscillation effect eliminating logic circuit and an output selection circuit. The input detection circuit receives an input signal from an external input terminal and outputs the detection signal. The oscillation effect eliminating logic circuit is coupled to the input detection circuit for reducing/eliminating oscillation effect and outputting the detection signal. The output selection circuit is coupled to the oscillation effect eliminating logic circuit to select and transmit either the output signal generated from the internal circuit or the detection signal to the output terminal.

Abstract translation: 提供了用于使振荡效应最小化的参数测量电路。 参数测量电路包括输入检测电路，振荡效应消除逻辑电路和输出选择电路。 输入检测电路从外部输入端接收输入信号并输出​​检测信号。 振荡效应消除逻辑电路耦合到输入检测电路，以减少/消除振荡效应并输出检测信号。 输出选择电路耦合到振荡效应消除逻辑电路，以将从内部电路产生的输出信号或检测信号发送到输出端子。

公开(公告)号：US07131079B2

公开(公告)日：2006-10-31

申请号：US10839534

申请日：2004-05-04

Applicant: Kun-Cheng Wu ,  Chien-Ming Huang ,  Chang-Chung Wu

Inventor： Kun-Cheng Wu ,  Chien-Ming Huang ,  Chang-Chung Wu

IPC: G06F17/50

CPC classification number: G06F17/5022

Abstract: A method of generating a protected standard delay format (SDF) file is disclosed. The interconnect delay descriptions of a SDF file are backwardly or forwardly integrated into the related cell delay descriptions according to their interconnection type to generate the protected SDF file. The total delay value of each signal path is the same as original, so that the simulation result generated by a simulator is not affected.

Abstract translation: 公开了一种生成受保护的标准延迟格式（SDF）文件的方法。 SDF文件的互连延迟描述根据其互连类型向后或向前集成到相关的单元延迟描述中，以生成受保护的SDF文件。 每个信号路径的总延迟值与原始路径相同，因此模拟器产生的仿真结果不受影响。

公开(公告)号：US07078930B2

公开(公告)日：2006-07-18

申请号：US10907608

申请日：2005-04-07

Applicant: Tin-Hao Lin ,  Chia-Nan Hong

Inventor： Tin-Hao Lin ,  Chia-Nan Hong

IPC: H03K19/00

CPC classification number: H01L22/34 ,  H01L2924/0002 ,  H01L2924/00

Abstract: An integrated circuit chip with a high area utilization rate includes: a plurality of logic circuits in a logic area; a first input and output circuit near a first side of the logic area for exchanging signals with the logic circuit; a second input and output circuit near a second side of the logic area for exchanging signals with the logic circuit; a plurality of first probe pads coupled to the first and the second input and output circuits for inputting or outputting signals to the first and the second input and output circuits; a corner cell comprising a plurality of wires coupled to the first and the second input and output circuits for exchanging signals between the first and the second input and output circuits; and a first process monitor circuit formed in the corner cell for monitoring a semiconductor process of the integrated circuit chip.

Abstract translation: 具有高面积利用率的集成电路芯片包括：逻辑区域中的多个逻辑电路; 靠近用于与逻辑电路交换信号的逻辑区域的第一侧的第一输入和输出电路; 靠近逻辑区域的第二侧的第二输入和输出电路，用于与逻辑电路交换信号; 耦合到第一和第二输入和输出电路的多个第一探针焊盘，用于向第一和第二输入和输出电路输入或输出信号; 角电池包括耦合到第一和第二输入和输出电路的多条导线，用于在第一和第二输入和输出电路之间交换信号; 以及形成在角电池中的用于监视集成电路芯片的半导体工艺的第一处理监视电路。

公开(公告)号：US07050282B2

公开(公告)日：2006-05-23

申请号：US10604362

申请日：2003-07-15

Applicant: Chien-Hui Chuang ,  Hung-Yi Chang ,  Yi-Hua Chang

Inventor： Chien-Hui Chuang ,  Hung-Yi Chang ,  Yi-Hua Chang

IPC: H02H3/00 ,  H02H7/00

CPC classification number: H01L27/0285 ,  H03K17/08104

Abstract: A power supply clamp circuit for preventing damage to an integrated circuit due to electrostatic discharge. The power supply clamp circuit includes a voltage generator electrically connected to a first node for generating a voltage; a first PMOS transistor having a source electrically connected to the first voltage source, a gate electrically connected to the first node, and a drain electrically connected to a second node; a first NMOS transistor having a drain electrically connected to the second node, a gate electrically connected to the first node, and a source connected to ground; a second NMOS transistor having a drain electrically connected to the first voltage source, a gate electrically connected to the second node, and a source connected to ground; and a second PMOS transistor having a source electrically connected to the second node, a gate and a drain commonly electrically connected to the first node.

Abstract translation: 一种电源钳位电路，用于防止由于静电放电而对集成电路造成的损坏。 电源钳位电路包括电连接到第一节点以产生电压的电压发生器; 第一PMOS晶体管，其具有电连接到第一电压源的源极，电连接到第一节点的栅极和电连接到第二节点的漏极; 第一NMOS晶体管，其具有电连接到第二节点的漏极，电连接到第一节点的栅极和连接到地的源极; 第二NMOS晶体管，其具有电连接到第一电压源的漏极，电连接到第二节点的栅极和连接到地的源极; 以及第二PMOS晶体管，其具有电连接到第二节点的源极，通常电连接到第一节点的栅极和漏极。

公开(公告)号：US07047347B2

公开(公告)日：2006-05-16

申请号：US10708174

申请日：2004-02-13

Applicant: Yu-Ping Feng

Inventor： Yu-Ping Feng

IPC: G06F13/20 ,  G06F13/38

CPC classification number: G06F13/32 ,  G06F2213/0042

Abstract: A data transfer method for a Universal Serial Bus (USB) device is provided. The data transfer rate of a bulk transfer transmission in the USB is detected first for selecting a transfer transmission having a better data transfer rate between the bulk transfer transmission in the USB and an interrupt transfer transmission in the USB, so as to ensure the data transfer bandwidth in the USB is better utilized by the USB device.

Abstract translation: 提供了一种用于通用串行总线（USB）设备的数据传输方法。 首先检测USB中的批量传输传输的数据传输速率，以选择在USB中的批量传送传输与USB中的中断传送传输之间具有更好的数据传输速率的传送传输，以确保数据传送 USB设备中更好地利用USB中的带宽。

公开(公告)号：US07036099B2

公开(公告)日：2006-04-25

申请号：US10626634

申请日：2003-07-25

Applicant: An-Ru Andrew Cheng ,  Chang-Song Lin ,  Tzu-Chun Liu ,  Huan-Yung Tseng

Inventor： An-Ru Andrew Cheng ,  Chang-Song Lin ,  Tzu-Chun Liu ,  Huan-Yung Tseng

IPC: G06F17/50

CPC classification number: G01R31/318538 ,  G01R31/31855

Abstract: An integrated circuit for locating failure process layers. The circuit has a substrate with a scan chain disposed therein, having scan cells connected to form a series chain. Each connection is formed according to a layout constraint of a minimum dimension provided by design rules for an assigned routing layer. Since the connection in the assigned routing layer is constrained to a minimum, the scan chain is vulnerable to variations in processes relevant to the assigned routing layer. The scan chain makes it easier to locate processes causing low yield rate of the scan chain.

Abstract translation: 用于定位故障过程层的集成电路。 电路具有设置在其中的扫描链的基板，其具有连接以形成串联链的扫描单元。 每个连接根据由分配的路由层的设计规则提供的最小维度的布局约束形成。 由于分配的路由层中的连接被限制到最小限度，扫描链很容易受到与分配的路由层相关的进程变化的影响。 扫描链使得更容易定位导致扫描链的低产率的过程。