公开(公告)号：US20080211021A1

公开(公告)日：2008-09-04

申请号：US12074226

申请日：2008-02-29

Applicant: Orazio Battiato ,  Domenico Repici ,  Fabrizio Marco Di Paola ,  Giuseppe Arena ,  Angelo Magri

Inventor： Orazio Battiato ,  Domenico Repici ,  Fabrizio Marco Di Paola ,  Giuseppe Arena ,  Angelo Magri

IPC: H01L29/78 ,  H01L21/336

CPC classification number: H01L29/7802 ,  H01L29/0856 ,  H01L29/0878 ,  H01L29/42368 ,  H01L29/42372 ,  H01L29/42376 ,  H01L29/66712 ,  H01L29/66719

Abstract: According to an embodiment of a method for manufacturing a MISFET device, in a semiconductor wafer, a semiconductor layer is formed, having a first type of conductivity and a first level of doping. A first body region and a second body region, having a second type of conductivity, opposite to the first type of conductivity, and an enriched region, extending between the first and second body regions are formed in the semiconductor layer. The enriched region has the first type of conductivity and a second level of doping, higher than the first level of doping. Moreover, a gate electrode is formed over the enriched region and over part of the first and second body regions, and a dielectric gate structure is formed between the gate electrode and the semiconductor layer, the dielectric gate structure having a larger thickness on the enriched region and a smaller thickness on the first and second body regions. To form the enriched region, a first conductive layer is made on the semiconductor layer, an enrichment opening is formed in the first conductive layer, and a dopant species is introduced into the semiconductor layer through the enrichment opening. Furthermore, the formation of the dielectric gate structure envisages filling the enrichment opening with dielectric material, prior to forming the first body region and the second body region.

Abstract translation: 根据用于制造MISFET器件的方法的实施例，在半导体晶片中，形成具有第一类型的导电性和第一级掺杂的半导体层。 在半导体层中形成有具有与第一类型的导电性相反的第二导电类型的第一体区和第二体区，以及在第一和第二体区之间延伸的富集区。 富集区具有第一类导电性和第二级掺杂，高于第一级掺杂。 此外，在富集区域和第一和第二体区的一部分之上形成栅电极，并且在栅极电极和半导体层之间形成介电栅极结构，在富集区域上具有较大厚度的电介质栅极结构 并且在第一和第二身体区域上具有较小的厚度。 为了形成富集区域，在半导体层上形成第一导电层，在第一导电层中形成富集开口，并且通过富集开口将掺杂剂物质引入半导体层。 此外，介电栅极结构的形成设想在形成第一体区域和第二体区域之前用电介质材料填充富集开口。

公开(公告)号：US20080151675A1

公开(公告)日：2008-06-26

申请号：US11963145

申请日：2007-12-21

Applicant: Cosimo Torelli ,  Danilo Rimondi ,  Rita Zappa

Inventor： Cosimo Torelli ,  Danilo Rimondi ,  Rita Zappa

IPC: G11C5/14

CPC classification number: G11C5/14 ,  G11C11/417

Abstract: An integrated circuit includes an array of memory cells arranged in a plurality of sectors. Each sector includes a plurality of distinct random access memory resources able to be accessed differently in different modes. Peripheral circuitry is commonly shared by at least some of the sectors for addressing and reading/writing data. A respective dedicated controllable power supply line is coupled to each sector.

Abstract translation: 集成电路包括布置在多个扇区中的存储单元的阵列。 每个扇区包括能够以不同模式被不同地访问的多个不同的随机存取存储器资源。 外围电路通常由用于寻址和读取/写入数据的至少一些扇区共享。 相应的专用可控电源线连接到每个扇区。

公开(公告)号：US20080104477A1

公开(公告)日：2008-05-01

申请号：US12001294

申请日：2007-12-10

Applicant: Massimiliano Lunelli ,  Rino Micheloni ,  Roberto Ravasio ,  Alessia Marelli

Inventor： Massimiliano Lunelli ,  Rino Micheloni ,  Roberto Ravasio ,  Alessia Marelli

IPC: H03M13/05 ,  G06F11/10

CPC classification number: H03M13/1575 ,  H03M13/13 ,  H03M13/15 ,  H03M13/19

Abstract: A method and system for making error corrections on digital information coded as symbol sequences, for example digital information stored in electronic memory systems or transmitted from and to these systems is described, provides the transmission of sequences incorporating a portion of error corrector code allowing the sequence which is more probably the original transmitted through the calculation of an error syndrome using a parity matrix to be restored when received. Advantageously according to embodiments of the invention, the error code incorporated in the original sequence belongs to a non Boolean group.

Abstract translation: 描述了一种用于对编码为符号序列的数字信息进行纠错的方法和系统，例如存储在电子存储器系统中或从这些系统发送的数字信息或从这些系统发送和传送到这些系统的数字信息，提供包含一部分误差校正码的序列的传输， 这更可能是通过使用在接收时要恢复的奇偶校验矩阵的误差校正子的计算来传送的。 有利地，根据本发明的实施例，并入原始序列中的错误代码属于非布尔组。

公开(公告)号：US20080024198A1

公开(公告)日：2008-01-31

申请号：US11495875

申请日：2006-07-28

Applicant: Davide Bitonti ,  Andrea Castaldo ,  Angela Foschini

Inventor： Davide Bitonti ,  Andrea Castaldo ,  Angela Foschini

IPC: G05F1/10

CPC classification number: H02M3/07

Abstract: A voltage booster for generating a boosted voltage, including a charge pump adapted to generate the boosted voltage starting from a supply voltage by a transfer of electric charge controlled by at least one oscillating signal having an oscillation frequency; an oscillator for providing the oscillating signal; and a regulation circuit arranged to receive and perform a comparison of a voltage related to the boosted voltage and a reference voltage, and adapted to provide at least one regulation signal indicative of a result of said comparison, wherein said regulation signal is fed to the oscillator to control said oscillation frequency. The regulation circuit is adapted to cause the at least one regulation signal take one among a plurality of discrete values, depending on the result of the comparison, so that the oscillation frequency of the at least one periodical signal accordingly can take one among a plurality of discrete oscillation frequency values.

Abstract translation: 一种用于产生升压电压的升压器，包括电荷泵，其适于通过由具有振荡频率的至少一个振荡信号控制的电荷的转移从电源电压开始产生升压电压; 用于提供振荡信号的振荡器; 以及调节电路，被布置成接收并执行与所述升压电压和参考电压相关的电压的比较，并且适于提供指示所述比较结果的至少一个调节信号，其中所述调节信号被馈送到所述振荡器 以控制所述振荡频率。 调节电路适于使得至少一个调节信号取决于比较结果的多个离散值中的一个，使得至少一个周期信号的振荡频率相应地可以采用多个 离散振荡频率值。

公开(公告)号：US20070286305A1

公开(公告)日：2007-12-13

申请号：US11725183

申请日：2007-03-16

Applicant: Stefano Saggini ,  Roberto Cappelletti ,  Walter Stefanutti ,  Paolo Mattavelli

Inventor： Stefano Saggini ,  Roberto Cappelletti ,  Walter Stefanutti ,  Paolo Mattavelli

IPC: H04L27/10

CPC classification number: H04B3/548 ,  H04B2203/5425 ,  H04B2203/547 ,  H04B2203/5483 ,  H04B2203/5491 ,  Y10T307/685

Abstract: A power converter having a noise component and a modulator configured to vary a frequency of the noise component of the power converter on the basis of a digital signal to be transmitted.

Abstract translation: 具有噪声分量的功率转换器和被配置为基于要发送的数字信号来改变功率转换器的噪声分量的频率的调制器。

公开(公告)号：US20070242541A1

公开(公告)日：2007-10-18

申请号：US11726993

申请日：2007-03-23

Applicant: Michele La Placa ,  Ignazio Martines

Inventor： Michele La Placa ,  Ignazio Martines

IPC: G11C7/02

CPC classification number: G11C7/067 ,  G11C11/5642 ,  G11C16/28 ,  G11C2207/063

Abstract: A sensing circuit for a semiconductor memory, comprising at least one detecting amplifier, said detecting amplifier comprising: a first circuital branch adapted to be electrically run through by a first current corresponding to the sum of a second current as a function of a comparison current and a cell current, said cell current being a function of a state of a memory cell to be read in a predetermined biasing condition; a second circuital branch coupled as a current mirror configuration with the first circuital branch, said second circuital branch being adapted in the operation to be run through by a third current proportional to the first current; a third circuital branch coupled to said second branch, said third circuital branch being adapted in the operation to sink a fourth current as a function of said comparison current; a fourth circuital branch coupled to said second and third circuital branches, said fourth circuital branch being adapted in the operation to be run through by a residual current equal to the difference between the third and the fourth current, said residual current assuming different values depending on the fact that the cell current is lower, equal or higher than the comparison current; residual current sensitive means adapted to generate an indication of the state of the memory cell as a function of a value of the residual current.

Abstract translation: 一种用于半导体存储器的感测电路，包括至少一个检测放大器，所述检测放大器包括：第一电路分支，其适于电流通过对应于作为比较电流的函数的第二电流的和的第一电流;以及 电池电流，所述电池电流是在预定偏置条件下要读取的存储器单元的状态的函数; 第二电路分支作为具有第一电路分支的电流反射镜配置耦合，所述第二电路分支适于在与第一电流成比例的第三电流的运行中运行; 耦合到所述第二分支的第三电路分支，所述第三电路分支适于作为所述比较电流的函数来吸收第四电流的操作; 耦合到所述第二和第三电路分支的第四电路分支，所述第四电路分支适于在所述操作中运行等于所述第三和第四电流之间的差的剩余电流，所述剩余电流取决于 电池电流低于等于或高于比较电流的事实; 剩余电流敏感装置适于根据剩余电流的值产生存储器单元的状态的指示。

公开(公告)号：US20070241804A1

公开(公告)日：2007-10-18

申请号：US11725988

申请日：2007-03-19

Applicant: Giovanni Campardo ,  Rino Micheloni

Inventor： Giovanni Campardo ,  Rino Micheloni

IPC: H03L5/00

CPC classification number: G11C5/145 ,  G11C7/1051 ,  G11C7/1057 ,  G11C7/1078 ,  G11C7/1084 ,  G11C8/08 ,  G11C16/08 ,  G11C16/12 ,  H03K3/356113

Abstract: A level shifter is proposed. The level shifter includes a stage having a first branch and a second branch, each branch including: a selection terminal for receiving a selection signal, the selection signal received by the first branch and the second branch being alternatively at a first voltage and at a second voltage higher than the first voltage in absolute value, a service terminal for receiving a third voltage higher than the second voltage in absolute value, an input circuit for coupling an intermediate node to the selection terminal when at the second voltage or for insulating the intermediate node from the selection terminal otherwise, an interface circuit for coupling an output terminal to the intermediate node when coupled or for insulating the output terminal from the intermediate node otherwise, and an output circuit for insulating the service terminal from the output terminal when coupled or for coupling the service terminal to the output terminal otherwise, the output terminals of the first branch and the second branch providing an output signal being alternatively at the second voltage or at the third voltage according to the selection signal.

Abstract translation: 提出了一种电平转换器。 电平移位器包括具有第一分支和第二分支的级，每个分支包括：选择终端，用于接收选择信号，由第一分支接收的选择信号和第二分支交替地处于第一电压和第二分支 电压高于绝对值中的第一电压，用于接收高于绝对值的第二电压的第三电压的服务终端，用于当处于第二电压时将中间节点耦合到选择端的输入电路或用于将中间节点 否则，从选择端子接收用于将输出端子耦合到中间节点或用于将输出端子与中间节点绝缘的接口电路，否则的接口电路，以及用于在连接或耦合时将服务终端与输出端子绝缘的输出电路 服务终端到输出端，否则，第一分支的输出端和 所述第二分支根据所述选择信号提供交替地处于所述第二电压或所述第三电压的输出信号。

公开(公告)号：US20070181933A1

公开(公告)日：2007-08-09

申请号：US11617472

申请日：2006-12-28

Applicant: Giorgio Servalli ,  Gianfranco Capetti ,  Pietro Cantu

Inventor： Giorgio Servalli ,  Gianfranco Capetti ,  Pietro Cantu

IPC: H01L29/76

CPC classification number: H01L27/115 ,  H01L27/0203 ,  H01L27/11521

Abstract: A non-volatile memory device integrated on semiconductor substrate and having a matrix of non-volatile memory cells organized in rows, called word lines, and columns, called bit lines, the device including a plurality of active areas formed on the semiconductor substrate equidistant from each other, and having at least a first and a second group of active areas; the non-volatile memory cells integrated in the first group of active areas, each non-volatile memory cell having a source region, a drain region, and a floating gate electrode coupled to a control gate electrode, at least one group of the memory cells sharing a common source region integrated on the semiconductor substrate; and a contact region integrated in the second group of active areas and provided with at least one common source contact of the common source region.

Abstract translation: 一种非易失性存储器件，集成在半导体衬底上并且具有被称为位线的被称为字线的行（称为字线）和列的非易失性存储器单元矩阵，该器件包括形成在半导体衬底上等距离的多个有源区 并且具有至少第一组和第二组活动区域; 集成在第一组有源区域中的非易失性存储单元，每个非易失性存储单元具有耦合到控制栅电极的源极区，漏极区和浮栅，至少一组存储单元 共享在半导体衬底上集成的公共源极区域; 以及集成在所述第二组有源区域中并且设置有所述公共源极区域的至少一个公共源极触点的接触区域。

公开(公告)号：US20070163815A1

公开(公告)日：2007-07-19

申请号：US11564182

申请日：2006-11-28

Applicant: Tommaso Ungaretti ,  Ernesto Lasalandra

Inventor： Tommaso Ungaretti ,  Ernesto Lasalandra

IPC: G08C21/00

CPC classification number: G01P15/125 ,  G01P15/131

Abstract: A detection circuit is provided with a differential capacitive sensor and with an interface circuit having a first sense input and a second sense input, electrically connected to the differential capacitive sensor. Provided in the interface circuit are: a sense amplifier connected at input to the first sense input and to the second sense input and supplying an output signal related to a capacitive unbalancing of the differential capacitive sensor; and a common-mode control circuit, connected to the first sense input and to the second sense input and configured to control a common-mode electrical quantity present on the first sense input and on the second sense input. The common-mode control circuit is of a totally passive type and is provided with a capacitive circuit, which is substantially identical to an equivalent electrical circuit of the differential capacitive sensor and is driven with a driving signal in phase opposition with respect to a read signal supplied to the differential capacitive sensor.

Abstract translation: 检测电路设置有差分电容传感器和具有电连接到差分电容传感器的具有第一感测输入和第二感测输入的接口电路。 提供在接口电路中的是：在输入端连接到第一感应输入和第二感测输入的感测放大器，并提供与差分电容传感器的电容性不平衡有关的输出信号; 以及共模控制电路，其连接到第一感测输入和第二感测输入，并被配置为控制存在于第一感测输入和第二感测输入上的共模电量。 共模控制电路是全无源型的，并且具有电容电路，该电容电路基本上与差动电容式传感器的等效电路相同，并且以与读取信号相反的驱动信号驱动 提供给差分电容传感器。

公开(公告)号：US20070157066A1

公开(公告)日：2007-07-05

申请号：US11324100

申请日：2005-12-29

Applicant: Andrea Concil ,  Andrea Giorgi ,  Stefano Valle

Inventor： Andrea Concil ,  Andrea Giorgi ,  Stefano Valle

IPC: H03M13/00

CPC classification number: H03M13/2957 ,  H03M13/3911 ,  H03M13/6502

Abstract: A method performs iterative decoding of information coded by an error correction code. The method includes: defining a transcendent first function representing a quantity to be evaluated for the decoding method; defining a quantized second function approximating the first function; computing first values of the second function obtained based on first arguments; the first values being not null and the first arguments being variable in a limited range having a maximum limit; computing second values of the second function obtained on the basis of second arguments, the second values being null; and generating a look-up table representing the first function and containing the first and second values associated to indexes correlated to said first arguments and to an expected maximum limit.

Abstract translation: 一种方法对由纠错码编码的信息执行迭代解码。 该方法包括：定义代表解码方法要评估的数量的超越第一函数; 定义近似第一函数的量化的第二函数; 计算基于第一参数获得的第二函数的第一值; 第一个值不为空，第一个参数在具有最大限制的有限范围内是可变的; 计算基于第二参数获得的第二函数的第二值，第二值为null; 以及生成表示第一函数并且包含与与所述第一参数相关联的索引相关联的第一和第二值的查找表和预期最大限制。