公开(公告)号：US07076598B2

公开(公告)日：2006-07-11

申请号：US10605099

申请日：2003-09-09

Applicant: Chih-Hung Wang

Inventor： Chih-Hung Wang

IPC: G06F12/00

CPC classification number: G06F12/0246 ,  G06F2212/7203

Abstract: A pipeline accessing method to a large block memory is described. The large block flash memory has a plurality of pages and each page has a plurality of sectors. The memory device has a controller to control an access operation between a host and a cell array of the large block flash memory with a page buffer. The controller includes at least two buffers, when the host intends to program the memory device. In the method, data sectors are transferred between the host and the large block flash memory by alternatively using the buffers. After transferring N data sectors with respect to one page, a start program command is issued by the controller for programming the data.

Abstract translation: 描述了对大块存储器的管道访问方法。 大块闪速存储器具有多个页面，并且每个页面具有多个扇区。 存储器装置具有控制器，用于通过页缓冲器来控制主块与大块闪存的单元阵列之间的访问操作。 当主机打算对存储器件进行编程时，控制器至少包括两个缓冲器。 在该方法中，通过交替地使用缓冲器，在主机和大块闪速存储器之间传送数据扇区。 在相对于一页传送N个数据扇区之后，由控制器发出用于编程数据的开始程序命令。

公开(公告)号：US07061042B2

公开(公告)日：2006-06-13

申请号：US10871170

申请日：2004-06-18

Applicant: Chien-Hsing Lee ,  Chin-Hsi Lin ,  Jhyy-Cheng Liou

Inventor： Chien-Hsing Lee ,  Chin-Hsi Lin ,  Jhyy-Cheng Liou

IPC: H01L29/788

CPC classification number: H01L27/11568 ,  G11C16/0483 ,  H01L27/115 ,  H01L27/11521 ,  H01L27/11524 ,  H01L29/7923

Abstract: A memory array device has a plurality of gate structure lines, adjacently disposed over a substrate along a direction, wherein at least a portion of the gate structure lines have memory function. A plurality of first doped regions, in the substrate at a side of a first line of the gate structure lines. A plurality of second doped regions, in the substrate at a side of a last line of the gate structure lines. Wherein the first doped regions and the second doped regions respectively for a plurality of pairs of doped region with respect to a plurality of bit lines. In other words, the conventional source/drain regions for each memory cell are saved. Instead, the gate lines are adjacently disposed together.

Abstract translation: 存储器阵列器件具有多个栅极结构线，沿着一个方向相邻地设置在衬底上，其中栅极结构线的至少一部分具有记忆功能。 多个第一掺杂区域，在栅极结构线的第一条线的一侧的衬底中。 在栅极结构线的最后一行的一侧的衬底中的多个第二掺杂区域。 其中第一掺杂区和第二掺杂区相对于多个位线分别用于多对掺杂区。 换句话说，每个存储单元的常规源/漏区被保存。 相反，栅极线相邻地放置在一起。

公开(公告)号：US06954376B2

公开(公告)日：2005-10-11

申请号：US10737413

申请日：2003-12-15

Applicant: Jhyy-Cheng Liou

Inventor： Jhyy-Cheng Liou

IPC: G11C5/02 ,  G11C5/06 ,  G11C16/04 ,  H01L21/8246 ,  H01L27/115

CPC classification number: H01L27/11568 ,  G11C16/0466 ,  H01L27/115

Abstract: A non-volatile memory array structure, comprising a plurality of first transistors, serving for memory function, being arranged to have a plurality of columns and a plurality of first rows. The first transistors in each column are coupled in series, and adjacent two of the columns are grouped into a memory group using a common bit line. The gate electrodes of the first transistors in the same first row are coupled with a first sequence word line. A plurality of second transistors are also included. Each of the second transistors is coupled between two columns of the memory group and is adjacent to each of the first rows. The second transistors form a plurality of second rows, wherein gate electrodes of the second transistors in the same second row are coupled to a second sequence word line.

公开(公告)号：US11206495B2

公开(公告)日：2021-12-21

申请号：US16677622

申请日：2019-11-07

Applicant: Solid State System Co., Ltd.

Inventor： Tsung-Min Hsieh ,  Li-Chi Tsao ,  Chien-Hsing Lee

IPC: H04R19/00 ,  H04R19/04 ,  B81B3/00 ,  B81C1/00 ,  H04R7/04 ,  H04R7/18

Abstract: A MEMS microphone includes a substrate. A dielectric layer is disposed on the substrate, having an opening and includes: indent region surrounding the opening; pillars extending from an indent surface at the indent region to the substrate; and an outer part surrounding the indent region and disposed on the substrate. A signal sensing space is created at the indent region between the pillars and between the pillars and the outer part. A first electrode layer is disposed on the indent surface of the dielectric layer. A second electrode layer is disposed on the substrate. A sensing diaphragm is held by the dielectric layer, including two elastic diaphragms supported by the dielectric layer; and a conductive plate between the first elastic diaphragm and the second elastic diaphragm. The conductive plate has a central part embedded in the holding structure and a peripheral part extending into the signal sensing space.

公开(公告)号：US20210276857A1

公开(公告)日：2021-09-09

申请号：US16812395

申请日：2020-03-09

Applicant: Solid State System Co., Ltd.

Inventor： Cheng-Wei Tsai ,  Tsung-Min Hsieh ,  Chien-Hsing Lee

IPC: B81B3/00 ,  H04R31/00 ,  B81C1/00 ,  H04R7/18

Abstract: The invention provides a MEMS microphone. The MEMS microphone includes a substrate, having a first opening. A dielectric layer is disposed on the substrate, wherein the dielectric layer has a second opening aligned to the first opening. A diaphragm is disposed within the second opening of the dielectric layer, wherein a peripheral region of the diaphragm is embedded into the dielectric layer at sidewall of the second opening. A backplate layer is disposed on the dielectric layer and covering over the second opening. The backplate layer includes a plurality of acoustic holes arranged into a regular array pattern. The regular array pattern comprises a pattern unit, the pattern unit comprises one of the acoustic holes as a center hole, and peripheral holes of the acoustic holes surrounding the center hole with a same pitch to the center hole.

公开(公告)号：US10728674B2

公开(公告)日：2020-07-28

申请号：US16112777

申请日：2018-08-27

Applicant: Solid State System Co., Ltd.

Inventor： Tsung-Min Hsieh ,  Li-Chi Tsao ,  Chien-Hsing Lee ,  Jhyy-Cheng Liou

IPC: H04R19/04 ,  B81B7/00 ,  B81C1/00 ,  H04R19/00 ,  H04R1/04

Abstract: A structure of micro-electro-mechanical-system (MEMS) microphone package includes a packaging substrate and an integrated circuit disposed on the packaging substrate. In addition, a MEMS microphone is disposed on the packaging substrate, wherein the MEMS microphone is electrically connected to the integrated circuit. A conductive adhesion layer is disposed on the packaging substrate, surrounding the integrated circuit and the MEMS microphone. A cap structure has a bottom part being adhered to the conductive adhesion layer. An underfill layer is disposed on the packaging substrate, covering an outer side of the conductive adhesion layer.

公开(公告)号：US09321635B2

公开(公告)日：2016-04-26

申请号：US14092929

申请日：2013-11-28

Applicant: Solid State System Co., Ltd.

Inventor： Tsung-Min Hsieh ,  Chien-Hsing Lee ,  Jhyy-Cheng Liou

IPC: H01L21/00 ,  B81C1/00

CPC classification number: B81C1/00928 ,  B81C1/00476

Abstract: A method for releasing a diaphragm of a micro-electro-mechanical systems (MEMS) device at a stage of semi-finished product. The method includes pre-wetting the MEMS device in a pre-wetting solution to at least pre-wet a sidewall surface of a cavity of the MEMS device. Then, a wetting process after the step of pre-wetting the MEMS device is performed to etch a dielectric material of a dielectric layer for holding the diaphragm, wherein a sensing portion of the diaphragm is released from the dielectric layer.

Abstract translation: 一种在半成品阶段释放微电子机械系统（MEMS）装置的隔膜的方法。 该方法包括将预先润湿溶液中的MEMS器件预润湿至少预先润湿MEMS器件的空腔的侧壁表面。 然后，执行在预先润湿MEMS器件的步骤之后的润湿过程，以蚀刻用于保持隔膜的电介质层的电介质材料，其中隔膜的感测部分从电介质层释放。

公开(公告)号：US09271087B1

公开(公告)日：2016-02-23

申请号：US14505495

申请日：2014-10-02

Applicant: Solid State System Co., Ltd.

Inventor： Tsung-Min Hsieh ,  Chien-Hsing Lee ,  Chih-Hsien Chung ,  Yong-Wei Chen ,  Jhyy-Cheng Liou

IPC: H04R25/00 ,  H04R23/00 ,  H04R31/00 ,  H04R19/00 ,  H04R19/04

CPC classification number: H04R23/006 ,  H04R19/005 ,  H04R19/04 ,  H04R31/00 ,  H04R2201/003

Abstract: A MEMS microphone package device includes a MEMS microphone chip as an integrated circuit chip. An acoustic sensing structure is embedded in the integrated circuit chip. An adhesive structure adheres on outer sidewall of the microphone chip. A bottom portion of the adhesive structure protrudes out from first surface of the microphone chip and adheres on a surface of a substrate, having interconnection structure, to form a first seal ring. A space between the acoustic sensing structure and the substrate and sealed by the first seal ring forms a second chamber. A cover adheres to top portion of the adhesive structure, covering over the cavity on the second surface of the microphone chip. The top portion of the adhesive structure forms as a second seal ring. A space between the cover and the second surface of the microphone chip and sealed by the second seal ring forms a first chamber.

Abstract translation: MEMS麦克风封装器件包括作为集成电路芯片的MEMS麦克风芯片。 声学感测结构嵌入在集成电路芯片中。 粘合剂结构粘附在麦克风芯片的外侧壁上。 粘合剂结构的底部从麦克风芯片的第一表面突出出来并粘附在具有互连结构的基板的表面上，以形成第一密封环。 在声学检测结构和衬底之间并由第一密封环密封的空间形成第二腔室。 盖子粘附到粘合剂结构的顶部，覆盖在麦克风芯片的第二表面上的空腔上。 粘合剂结构的顶部形成为第二密封环。 所述盖和麦克风芯片的第二表面之间的空间被第二密封环密封形成第一腔室。

公开(公告)号：US09264832B2

公开(公告)日：2016-02-16

申请号：US14066712

申请日：2013-10-30

Applicant: Solid State System Co., Ltd.

Inventor： Cheng-Wei Tsai ,  Chien-Hsing Lee ,  Jhyy-Cheng Liou

IPC: H01L21/00 ,  H04R31/00 ,  H04R19/00

CPC classification number: H04R31/00 ,  H01L2224/48137 ,  H01L2924/16151 ,  H01L2924/16152 ,  H04R19/005 ,  H04R2201/003

Abstract: A method to protect an acoustic port of a microelectromechanical system (MEMS) microphone is provided. The method includes: providing the MEMS microphone; and forming a protection film, on the acoustic port of the MEMS microphone. The protection film has a porous region over the acoustic port to receive an acoustic signal but resist at least an intruding material. The protection film can at least endure a processing temperature of solder flow.

Abstract translation: 提供了保护微机电系统（MEMS）麦克风的声学端口的方法。 该方法包括：提供MEMS麦克风; 并在MEMS麦克风的声学端口上形成保护膜。 保护膜在声学端口上方具有多孔区域以接收声信号，但是至少阻挡入侵材料。 保护膜至少可以承受焊料流动的处理温度。

公开(公告)号：US08713242B2

公开(公告)日：2014-04-29

申请号：US12981499

申请日：2010-12-30

Applicant: Chih-Hung Wang ,  Chao-Han Wu ,  Ting-Chung Hu

Inventor： Chih-Hung Wang ,  Chao-Han Wu ,  Ting-Chung Hu

IPC: G06F12/02

CPC classification number: G06F12/0246

Abstract: A control method and an allocation structure for a flash memory device are provided herein. The flash memory device has a first memory module and a second memory module. Physical blocks of the first memory module and physical blocks of the second memory module are respectively divided into a plurality of groups, each of which has a plurality of the physical blocks. A first subunit and a second subunit of a first allocation unit are interleavingly written into a first group of the groups of the first memory module and a second group of the groups of the second memory chip respectively. Additionally, a first subunit and a second subunit of a second allocation unit are interleavingly written into a third group of the groups of the first memory module and the second group, respectively.

Abstract translation: 本文提供了一种用于闪速存储器件的控制方法和分配结构。 闪存设备具有第一存储器模块和第二存储器模块。 第一存储器模块的物理块和第二存储器模块的物理块分别被分成多个组，每个组具有多个物理块。 第一分配单元的第一子单元和第二子单元分别被交织地写入第一存储器模块的组的第一组和第二存储器芯片的组的第二组。 此外，第二分配单元的第一子单元和第二子单元分别被交织地写入第一存储器模块和第二组的组的第三组中。