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    LAYER-3 PERFORMANCE MONITORING SECTIONALIZATION
    55.
    发明申请
    LAYER-3 PERFORMANCE MONITORING SECTIONALIZATION 审中-公开

    公开(公告)号：US20190075039A1

    公开(公告)日：2019-03-07

    申请号：US16177346

    申请日：2018-10-31

    Applicant: Accedian Networks Inc.

    Inventor： Claude Robitaille

    IPC: H04L12/26 ,  H04L29/08

    CPC classification number: H04L43/50 ,  H04L43/0829 ,  H04L43/0835 ,  H04L43/0841 ,  H04L43/0864 ,  H04L69/324 ,  H04L69/325

    Abstract: A method is disclosed for the collection of performance metrics by establishing service operations administration and maintenance (OAM) sessions between an actuator and a plurality of reflectors in a communication network. Test packets from an actuator simultaneously reach a plurality of reflectors along a test path. Each single test packet results into a plurality of test results, one per reflector, with quasi-synchronous performance metrics to sectionalize a network and more efficiently isolate fault or performance problems without the need for additional test packets to isolate the issue. Another method is disclosed wherein an actuator generates and transmits a plurality of simultaneous test packets, one per NID device, resulting into a plurality of test results, one per reflector, with quasi-synchronous performance metrics to sectionalize a network and more efficiently isolate fault or performance problems without the need for additional test packets to isolate the issue.

    HEURISTICS FOR SELECTING NEAREST ZONE BASED ON ICA RTT AND NETWORK LATENCY
    56.
    发明申请
    HEURISTICS FOR SELECTING NEAREST ZONE BASED ON ICA RTT AND NETWORK LATENCY 审中-公开

    公开(公告)号：US20190037011A1

    公开(公告)日：2019-01-31

    申请号：US15661296

    申请日：2017-07-27

    Applicant: Citrix Systems, Inc.

    Inventor： Kiran Kumar

    IPC: H04L29/08 ,  H04L12/24 ,  H04L12/26 ,  H04L12/727

    CPC classification number: H04L67/101 ,  H04L41/0893 ,  H04L41/12 ,  H04L41/5051 ,  H04L41/5096 ,  H04L43/04 ,  H04L43/0864 ,  H04L43/16 ,  H04L45/121

    Abstract: Described embodiments provide systems and methods for zone selection for distributed services. A device records latency data measured for interactions between each of a plurality of clients and a service hosted by servers in two or more zones. The device directs network communications from each of the plurality of clients to respective servers hosting the service based on zones assigned to each of the plurality of clients. The device assigns clients to zones based on the recorded latency data. For example, the device identifies a grouping for a client, determines whether the recorded latency data indicates that latency for clients in the grouping is increasing faster than a threshold rate, and selects, responsive to the determination, a zone indicated by a selected set of recorded latency data as lowest in latency.

    Buffer Sizing of a NoC Through Machine Learning
    59.
    发明申请
    Buffer Sizing of a NoC Through Machine Learning 审中-公开

    公开(公告)号：US20180324113A1

    公开(公告)日：2018-11-08

    申请号：US16037924

    申请日：2018-07-17

    Applicant: NetSpeed Systems, Inc.

    Inventor： Eric NORIGE ,  Nishant RAO ,  Sailesh KUMAR

    IPC: H04L12/861 ,  H04L12/24

    CPC classification number: H04L49/9005 ,  H04L41/14 ,  H04L41/145 ,  H04L43/0864 ,  H04L43/0894 ,  H04L43/16 ,  H04L49/109 ,  H04L49/30

    Abstract: The present disclosure is directed to buffer sizing of NoC link buffers by utilizing incremental dynamic optimization and machine learning. A method for configuring buffer depths associated with one or more network on chip (NoC) is disclosed. The method includes deriving characteristics of buffers associated with the one or more NoC, determining first buffer depths of the buffers based on the characteristics derived, obtaining traces based on the characteristics derived, measuring trace skews based on the traces obtained, determining second buffer depths based on the trace skews measured, optimizing the buffer depths associated with the network on chip (NoC) based on the second buffer depths, and configuring the buffer depths associated with one or more network on chip (NoC) based on the buffer depths optimized.

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