公开(公告)号：US07180949B2

公开(公告)日：2007-02-20

申请号：US10439571

申请日：2003-05-16

申请人： Bendik Kleveland ,  Eric Anderson ,  Gunes Aybay ,  Philip Ferolito

发明人： Bendik Kleveland ,  Eric Anderson ,  Gunes Aybay ,  Philip Ferolito

IPC分类号： H04L27/00 ,  H04L25/00 ,  H04L25/06

CPC分类号： H04L25/45 ,  H04L7/0008 ,  H04L7/005 ,  H04L7/046 ,  H04L25/028 ,  H04L25/0292

摘要： A high-speed parallel interface for communicating data between integrated circuits is disclosed. The interface is implemented by a transmitter and receiver pair and a single-ended parallel interconnect bus coupling to the transmitter and receiver pair. As opposed to transmitting small swing signals over differential signal lines, the transmitter transmits data to the receiver at full swing over the single-ended parallel interconnect bus. The invention can be implemented with simple CMOS circuitry that does not consume large die area. Accordingly, many link interfaces can be implemented on a single chip to provide a large data bandwidth.

摘要翻译： 公开了一种用于在集成电路之间传送数据的高速并行接口。 该接口由发射机和接收机对以及耦合到发射机和接收机对的单端并行互连总线来实现。 与通过差分信号线发送小的摆动信号相反，发射器在单端并行互连总线上全速摆放数据到接收机。 本发明可以用不消耗大的管芯面积的简单的CMOS电路来实现。 因此，可以在单个芯片上实现许多链路接口以提供大的数据带宽。

公开(公告)号：US20060227911A1

公开(公告)日：2006-10-12

申请号：US11101258

申请日：2005-04-06

申请人： Steven Millman ,  Dejan Mijuskovic ,  Jeffrey Porter

发明人： Steven Millman ,  Dejan Mijuskovic ,  Jeffrey Porter

IPC分类号： H04B1/10 ,  H04L7/00

CPC分类号： H04L7/042 ,  H04L7/005 ,  H04L7/0337

摘要： A system and method is provided for bit eye center retraining. In general, the system samples an incoming data stream to determine where transitions in the data stream occur, selectively compares the location of the transitions to the expected locations to produce difference values, and combines pairs of difference values to determine when the sample point of the data stream needs to be adjusted.

摘要翻译： 提供了一种用于位眼中心再训练的系统和方法。 通常，系统对输入数据流进行采样以确定数据流中的转换位置的发生，选择性地将转换的位置与预期位置进行比较以产生差分值，并且组合差分值对以确定何时 数据流需要调整。

公开(公告)号：US07117126B2

公开(公告)日：2006-10-03

申请号：US09946217

申请日：2001-09-05

申请人： Michael Stephen Floyd ,  Ravi Kumar Arimilli ,  Daniel Mark Dreps ,  Frank David Ferraiolo ,  Kevin F. Reick

发明人： Michael Stephen Floyd ,  Ravi Kumar Arimilli ,  Daniel Mark Dreps ,  Frank David Ferraiolo ,  Kevin F. Reick

IPC分类号： G06F11/30

CPC分类号： H04L7/02 ,  H04L1/24 ,  H04L7/0004 ,  H04L7/0008 ,  H04L7/005

摘要： A data processing system includes a mechanism to periodically idle the normal system operation to allow recalibration of its interface circuitry by transmission of data with transitions and logic levels indicative of actual operation. Provision is made to protect actual data of the system from corruption during recalibration.

公开(公告)号：US20060215782A1

公开(公告)日：2006-09-28

申请号：US11089216

申请日：2005-03-24

申请人： Yasser Ahmed ,  Robert Brink ,  Gregory Sheets ,  Lane Smith

发明人： Yasser Ahmed ,  Robert Brink ,  Gregory Sheets ,  Lane Smith

IPC分类号： H04L27/10

CPC分类号： H04L7/0012 ,  H04J3/0638 ,  H04L7/005

摘要： An integrated circuit device for use in a node of a communication system is provided. The integrated circuit device includes a memory configured to store data written thereto by a receiver associated with the node in accordance with a receiver clock, and to read data therefrom by a transmitter associated with the node in accordance with a transmitter clock. The integrated circuit device also includes a control logic circuit that is in communication with the memory, and is configured to send a control signal to the transmitter to adjust a speed of the transmitter clock responsive to an operating condition of the memory.

摘要翻译： 提供一种在通信系统的节点中使用的集成电路装置。 集成电路装置包括被配置为存储由根据接收机时钟与节点相关联的接收机写入的数据的存储器，并且根据发射机时钟由与节点相关联的发射机从其读取数据。 集成电路装置还包括与存储器通信的控制逻辑电路，并且被配置为响应于存储器的操作条件向发射器发送控制信号以调整发射机时钟的速度。

公开(公告)号：US07113562B1

公开(公告)日：2006-09-26

申请号：US09749270

申请日：2000-12-27

申请人： David S. Dunning ,  Chamath Abhayagunawardhana ,  Kenneth Drottar ,  Richard S. Jensen

发明人： David S. Dunning ,  Chamath Abhayagunawardhana ,  Kenneth Drottar ,  Richard S. Jensen

IPC分类号： H03D3/24 ,  H04L7/02

CPC分类号： H04L25/068 ,  H03D3/006 ,  H04L7/005 ,  H04L7/0331

摘要： Conventional receiver architectures are based on either frequency/phase tracking or oversampling. Both receiver types typically employ sensitive analog circuits, which create noise, consume power and utilize valuable space in their implementation. The invention adopts a novel approach to phase/frequency tracking that utilizes the edges or zero crossings of the input data waveform to effectively track the remote transmitter clock phase/frequency. This methodology minimizes the use of analog circuitry, thereby reducing the noise domain and the substrate space required for implementation of a tracking device.

摘要翻译： 传统的接收机架构基于频率/相位跟踪或过采样。 两种接收机类型通常采用灵敏的模拟电路，它们产生噪声，消耗功率并在其实现中利用有价值的空间。 本发明采用新颖的相位/频率跟踪方法，利用输入数据波形的边缘或过零点有效跟踪远程发射机时钟相位/频率。 该方法最大限度地减少了模拟电路的使用，从而降低了实现跟踪设备所需的噪声区域和衬底空间。

公开(公告)号：US20060193395A1

公开(公告)日：2006-08-31

申请号：US11055817

申请日：2005-02-11

申请人： Frank Ferraiolo ,  Robert Reese ,  Michael Spear

发明人： Frank Ferraiolo ,  Robert Reese ,  Michael Spear

IPC分类号： H04L5/12

CPC分类号： H04L25/14 ,  H04L7/0008 ,  H04L7/0037 ,  H04L7/005 ,  H04L7/044 ,  H04L7/046 ,  H04L7/10

摘要： An interface alignment pattern for de-skewing data bits received on an elastic interface is disclosed. The interface alignment pattern is “busy” in that it has a high number of logic state transitions. The busy interface alignment pattern can be used for scrambling and unscrambling operational data. The interface alignment pattern has a unique timing sequence for determining the location of a data bit's first data beat.

摘要翻译： 公开了一种用于在弹性接口上接收的用于去偏斜数据比特的接口对准模式。 接口对齐模式是“忙”，因为它具有大量的逻辑状态转换。 忙接口对准模式可用于加扰和解扰操作数据。 接口对准模式具有用于确定数据位的第一数据节拍位置的唯一定时序列。

公开(公告)号：US20060176970A1

公开(公告)日：2006-08-10

申请号：US10540682

申请日：2003-12-22

申请人： Yanzhong Dai ,  Luzhou Xu

发明人： Yanzhong Dai ,  Luzhou Xu

IPC分类号： H04L1/02

CPC分类号： H01Q21/28 ,  H01Q1/242 ,  H04B7/0848 ,  H04L7/005

摘要： A mobile terminal with smart antennas, comprises a plurality of groups of radio frequency signal processing modules (300), for transforming received multi-channel radio frequency signals to multi- channel baseband signals; a smart antenna processing module (306), for smart antenna baseband processing said multi-channel baseband signals output from said plurality of groups of radio frequency signal processing module so as to combine said multi- channel baseband signals into single-channel baseband signals, according to control information received one-off as said smart antenna processing module is enabled; and a baseband processing module (303-305), for providing said control information to said smart antenna processing module according to data from said smart antenna processing module, and baseband processing said single-channel baseband signals outputted from said smart antenna processing module.

摘要翻译： 具有智能天线的移动终端包括多组射频信号处理模块（300），用于将接收到的多频道射频信号变换成多信道基带信号; 智能天线处理模块（306），用于智能天线基带处理从所述多组射频信号处理模块输出的所述多通道基带信号，以便将所述多通道基带信号组合成单通道基带信号，根据 在所述智能天线处理模块被使能时控制一次性接收的信息; 以及根据来自所述智能天线处理模块的数据向所述智能天线处理模块提供所述控制信息以及从所述智能天线处理模块输出的所述单通道基带信号的基带处理的基带处理模块（303〜305）。

公开(公告)号：US07054356B2

公开(公告)日：2006-05-30

申请号：US10109286

申请日：2002-03-28

申请人： Mark A Wahl

发明人： Mark A Wahl

IPC分类号： H04L5/16

CPC分类号： G01R31/31715 ,  G01R31/31716 ,  H04L7/005 ,  H04L7/041

摘要： A method and apparatus for testing a serial connection is presented. A serial data stream is transmitted from a sending device to a receiving device. The serial data stream is generated using sending device timing information and input data. A receiver in the receiving device recovers both the timing information and the input data and then inputs them back into a transmitter located in the receiving device. The transmitter in the receiving device then generates a second serial data stream based on the recovered input data and the sending device timing information. A receiver in the sending device receives the second serial data stream and outputs the sending device timing information and input data to a FIFO buffer, for alignment of the input data. Since the input data and timing information are generated based on a sending device timing information, the FIFO can provide a signal for testing by performing phase alignment on the data. There is no need to re-synchronize the data in the sending device. Using the sending device timing information to generate and test information in the sending device, removes the need to test data using a FIFO in the receiving device and reduces the complexity and processing requirements of the FIFO in the sending device.

公开(公告)号：US20060072625A1

公开(公告)日：2006-04-06

申请号：US10948777

申请日：2004-09-23

申请人： Robert Shearer ,  Craig Wigglesworth

发明人： Robert Shearer ,  Craig Wigglesworth

IPC分类号： H04J3/06

CPC分类号： G06F13/4282 ,  G06F2213/0038 ,  H04L7/005 ,  H04L27/0014 ,  H04L2027/0073

摘要： Methods and apparatus that may be utilized in an effort to ensure bytes of data sequentially received on multiple single-byte data paths with properly aligned when presented on a multi-byte interface are provided. A sufficient number of bytes received each channel may be stored (e.g., buffered) and examined to properly match data from each single-byte path. Once matched, the data may be output in a proper order on the multi-byte interface, for example, via some type of multiplexor arrangement.

公开(公告)号：US20060023825A1

公开(公告)日：2006-02-02

申请号：US11057146

申请日：2005-02-15

申请人： Shinya Kato ,  Takayoshi Kyono ,  Ryuichi Nisiyama ,  Jin Takahashi

发明人： Shinya Kato ,  Takayoshi Kyono ,  Ryuichi Nisiyama ,  Jin Takahashi

IPC分类号： H04L25/00

CPC分类号： H04L7/0331 ,  G06F13/4273 ,  H04L7/005 ,  H04L25/14

摘要： A data transmitter and a data receiver generate respective synchronous signals from a common reference signal. The data receiver adjusts a phase of a first clock signal using each one of one-bit data signals each consisting of a single bit of received parallel data, so that a setup time and a hold time are ensured for the each one-bit data signal, and loads each one-bit data signal into a data buffer in accordance with the adjusted clock signal. Then, the data receiver reads the data held in the data buffer, in accordance with a second clock signal and in synchronization with the receiver synchronous signal. A memory position where the data signal is to be loaded is initialized when a training pattern transmitted in synchronization with the transmitter synchronous signal is detected.

摘要翻译： 数据发送器和数据接收器从公共参考信号产生相应的同步信号。 数据接收器使用每个由接收到的并行数据的单个比特构成的1比特数据信号中的每一个来调整第一时钟信号的相位，从而确保每一比特数据信号的建立时间和保持时间 并根据调整后的时钟信号将每一位数据信号加载到数据缓冲器中。 然后，数据接收机根据第二时钟信号并与接收机同步信号同步地读取保存在数据缓冲器中的数据。 当检测到与发射机同步信号同步发送的训练模式时，初始化要加载数据信号的存储器位置。