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1.发明授权公开(公告)号：US07113562B1
公开(公告)日：2006-09-26
申请号：US09749270
申请日：2000-12-27
CPC分类号： H04L25/068 , H03D3/006 , H04L7/005 , H04L7/0331
摘要： Conventional receiver architectures are based on either frequency/phase tracking or oversampling. Both receiver types typically employ sensitive analog circuits, which create noise, consume power and utilize valuable space in their implementation. The invention adopts a novel approach to phase/frequency tracking that utilizes the edges or zero crossings of the input data waveform to effectively track the remote transmitter clock phase/frequency. This methodology minimizes the use of analog circuitry, thereby reducing the noise domain and the substrate space required for implementation of a tracking device.
摘要翻译： 传统的接收机架构基于频率/相位跟踪或过采样。 两种接收机类型通常采用灵敏的模拟电路，它们产生噪声，消耗功率并在其实现中利用有价值的空间。 本发明采用新颖的相位/频率跟踪方法，利用输入数据波形的边缘或过零点有效跟踪远程发射机时钟相位/频率。 该方法最大限度地减少了模拟电路的使用，从而降低了实现跟踪设备所需的噪声区域和衬底空间。
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公开(公告)号：US06917659B1
公开(公告)日：2005-07-12
申请号：US09749269
申请日：2000-12-27
CPC分类号： H04L7/0054 , H04L7/005 , H04L7/0337
摘要： A method of recovering data from a modulated data signal includes tracking a transmitted clock with a plurality of locally-generated clock phases, estimating an average phase of previously detected edges, registering a pulse edge in the received stream of data at a transition phase corresponding to one of the plurality of locally-generated clock phases, determining whether a first symbol was received multiple times consecutively prior to the registered pulse edge, and using the determination of whether the first symbol was received multiple times consecutively in a receiver decision process.
摘要翻译： 从调制数据信号恢复数据的方法包括利用多个本地生成的时钟相位跟踪传输的时钟，估计先前检测到的边沿的平均相位，在所接收的数据流中在对应于 所述多个本地生成的时钟相位中的一个，确定在所述注册的脉冲沿之前连续地多次接收到第一符号，并且使用在所述接收机决定处理中是否连续地接收到所述第一符号的确定。
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公开(公告)号：US07054374B1
公开(公告)日：2006-05-30
申请号：US09752813
申请日：2000-12-29
CPC分类号： H04L5/1423 , H04L7/0079 , H04L7/0087 , H04L7/0338
摘要： When signaling over cables or other media having significant return impedance, it is generally more efficient to use two conductors to carry two simultaneous bi-directional signals differentially, rather than utilizing unidirectional communications. Bi-directional communications increases the aggregate bandwidth of a pair of conductors. A conversion circuit converts unidirectional signaling between an edge-based receiver and a transmitter to simultaneous differential bi-directional signaling. A receiver for receiving data includes an edge processor operative to make decisions using edges of a received data stream and a communication circuit coupled to the edge processor. The communication circuit is operative to convert communications with the edge processor from a first format, such as unidirectional signaling, to a second format, such as differential bi-directional signaling.
摘要翻译： 当通过电缆或具有显着回波阻抗的其它介质发信号时，使用两个导体差分地携带两个同时的双向信号通常更有效，而不是利用单向通信。 双向通信增加了一对导体的总带宽。 转换电路将基于边缘的接收机和发射机之间的单向信令转换为同步差分双向信令。 用于接收数据的接收机包括边缘处理器，其可操作以使用接收到的数据流的边缘和耦合到边缘处理器的通信电路进行判定。 通信电路可操作以将与边缘处理器的通信从诸如单向信令的第一格式转换为诸如差分双向信令的第二格式。
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4.发明授权公开(公告)号：US07280629B2
公开(公告)日：2007-10-09
申请号：US10969737
申请日：2004-10-19
CPC分类号： H04L25/068 , H03D3/006 , H04L7/005 , H04L7/0331
摘要： Conventional receiver architectures are based on either frequency/phase tracking or oversampling. Both receiver types typically employ sensitive analog circuits, which create noise, consume power and utilize valuable space in their implementation. The invention adopts a novel approach to phase/frequency tracking that utilizes the edges or zero crossings of the input data waveform to effectively track the remote transmitter clock phase/frequency. This methodology minimizes the use of analog circuitry, thereby reducing the noise domain and the substrate space required for implementation of a tracking device.
摘要翻译： 传统的接收机架构基于频率/相位跟踪或过采样。 两种接收机类型通常采用灵敏的模拟电路，它们产生噪声，消耗功率并在其实现中利用有价值的空间。 本发明采用新颖的相位/频率跟踪方法，利用输入数据波形的边缘或过零点有效跟踪远程发射机时钟相位/频率。 该方法最大限度地减少了模拟电路的使用，从而降低了实现跟踪设备所需的噪声区域和衬底空间。
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5.发明授权Method and apparatus for a tracking data receiver compensating for deterministic jitter 有权跟踪数据接收机补偿确定性抖动的方法和装置公开(公告)号：US06765975B2
公开(公告)日：2004-07-20
申请号：US09741319
申请日：2000-12-19
IPC分类号： H04L2536
CPC分类号： H04L7/0338 , H04L7/033
摘要： A tracking data receiver which can compensate for deterministic jitter is disclosed. The device utilizes a history of past data received to determine which of multiple samples taken within a bit period to utilize. Due to deterministic jitter that can occur in data signal communication, the delay of waveform development varies with the ratio of 0's to 1's transmitted prior to the bit period being observed. The present invention exploits the predictable nature of the deterministic jitter to decide which sample to choose.
摘要翻译： 公开了可补偿确定性抖动的跟踪数据接收机。 该设备利用接收到的过去数据的历史来确定在一个位周期内采用的多个样本中的哪个采样。 由于可能发生在数据信号通信中的确定性抖动，波形发展的延迟随着观察到比特周期之前发送的0到1的比率而变化。 本发明利用确定性抖动的可预测性来决定要选择哪个样本。
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公开(公告)号：US06606360B1
公开(公告)日：2003-08-12
申请号：US09475505
申请日：1999-12-30
IPC分类号： H04L700
CPC分类号： H04L7/0338
摘要： A method and apparatus for asynchronously receiving a stream of data. The method and apparatus operate to detect edges within the stream of data and track a transmitted clock using multiple locally-generated clock phases. Moreover, the method and apparatus determine whether each edge arrives early or late relative to an expected arrival time and use the determination whether an edge arrived early or late in a receiver decision process. An exemplary embodiment of the apparatus to recover a clock from a stream of data includes an edge buffer, an edge processor, a multi-phase clock and an elastic buffer. The edge buffer receives the data stream and outputs an edge signal that indicates detection of an edge within the data stream. The edge processor is coupled to the edge buffer, determines an average phase of the detected edges and outputs a data signal and the average phase. The multi-phase clock is coupled to the edge processor, and outputs a multiple clock phases offset from each other by a predetermined amount. The elastic buffer is coupled to the edge processor and the multi-phase clock and outputs the data and the average phase.
摘要翻译： 一种用于异步接收数据流的方法和装置。 所述方法和装置用于检测数据流内的边缘并且使用多个本地生成的时钟相位来跟踪发送的时钟。 此外，该方法和装置确定每个边缘是否相对于预期到达时间早到或晚进行，并且使用确定边缘在接收机决策过程中是早到还是迟。 从数据流恢复时钟的装置的示例性实施例包括边缘缓冲器，边缘处理器，多相时钟和弹性缓冲器。 边缘缓冲器接收数据流并输出指示检测数据流内的边缘的边缘信号。 边缘处理器耦合到边缘缓冲器，确定检测到的边缘的平均相位并输出数据信号和平均相位。 多相时钟耦合到边缘处理器，并输出多个时钟相位彼此偏移预定量。 弹性缓冲器耦合到边缘处理器和多相时钟并输出数据和平均相位。
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7.发明授权Method and apparatus for controlling the flow of data between servers using optimistic transmitter 有权使用乐观发射机控制服务器之间的数据流的方法和装置公开(公告)号：US06760307B2
公开(公告)日：2004-07-06
申请号：US09141134
申请日：1998-08-27
IPC分类号： H04L1228
CPC分类号： H04L1/0057 , H04L1/08 , H04L1/1635 , H04L1/1806 , H04L1/1835 , H04L1/1877 , H04L1/188 , H04L1/1883 , H04L41/06 , H04L47/10 , H04L47/17 , H04L47/26 , H04L2001/0096 , H04L2001/0097
摘要： Link-based flow control requires each link transmitter to retain packets until such time as they are acknowledged by the link receiver. Depending on the type of acknowledge, the transmitter will then either retry or de-allocate the packets. To improve throughput, the present invention includes an optimistic transmitter, which transmits packets without knowing the state of the receiver buffer. By so doing, the present invention improves the latency caused by delays in transit time between nodes. Furthermore, single acknowledgments are used to indicate successful receipt of multiple packets. Single negative acknowledgments are used to indicate successful receipt of all data between a last acknowledged data packet and a packet associated with the negative acknowledgment, which was received with errors.
摘要翻译： 基于链路的流量控制要求每个链路发送器保留分组，直到它们被链路接收机确认为止。 根据应答的类型，发射机将会重试或取消分配数据包。 为了提高吞吐量，本发明包括一种乐观的发送器，其在不知道接收器缓冲器的状态的情况下发送分组。 通过这样做，本发明改善了由节点之间的传送时间延迟引起的等待时间。 此外，单个确认用于指示成功接收多个分组。 单个否定确认用于指示在最后确认的数据分组和与否定确认相关联的分组之间的所有数据的成功接收，该分组被错误地接收。
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公开(公告)号：US06781434B2
公开(公告)日：2004-08-24
申请号：US10247752
申请日：2002-09-19
IPC分类号： H03K1730
CPC分类号： G11C27/024 , G11C27/026 , H03K17/162
摘要： A switch circuit having low charge dumping characteristics includes multiple parallel connected switching transistors and one or more associated cancellation transistors. The switching transistors perform basic switching functions within the switch circuit in response to a digital signal. During transitions of the digital signal, the switching transistors dump charge on an output node thereof due to parasitic capacitances within the devices. The cancellation transistor(s) dumps charge of an opposite polarity on the output node to cancel the charge dumped by the switching transistors. Two switching transistors are used for each cancellation transistor so that equal sized devices can be used throughout the switch circuit.
摘要翻译： 具有低电荷倾倒特性的开关电路包括多个并联的开关晶体管和一个或多个相关联的消除晶体管。 开关晶体管响应于数字信号在开关电路内执行基本的开关功能。 在数字信号的转换期间，开关晶体管由于器件内的寄生电容而在其输出节点上转储电荷。 消除晶体管在输出节点处转移相反极性的电荷，以消除由开关晶体管倾倒的电荷。 两个开关晶体管用于每个消除晶体管，使得在整个开关电路中可以使用等大小的器件。
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公开(公告)号：US06446235B1
公开(公告)日：2002-09-03
申请号：US09386474
申请日：1999-08-31
IPC分类号： G06F1110
CPC分类号： H04L1/0061 , H03M13/09 , H04L1/0041
摘要： An error detection technique uses a cumulative error detecting code (such as a cumulative CRC checksum or the like). At the source node (transmitter side) an error detecting code of a previous cell is stored. The next cell to be transmitted is received and the error detecting code of the previous cell is appended to the next cell. A next error detecting code is calculated as a function of at least a portion of the next cell to be transmitted and the previous error detecting code appended thereto. The previous error detecting code appended to the next cell is replaced with the next error detecting code, and the next cell including the next error detecting code appended thereto is transmitted. In this manner, the cumulative error detecting code is calculated over the current cell and a previous error detecting code. Thus, the cumulative error detecting code can be used to detect bit errors in each individual cell as well as to detect one or more missing or dropped cells.
摘要翻译： 错误检测技术使用累积检错码（如累积CRC校验和等）。 在源节点（发射机侧），存储先前小区的错误检测码。 接收到要发送的下一个小区，并将上一个小区的错误检测码追加到下一个小区。 根据要发送的下一个小区的至少一部分和附加的先前的错误检测码，计算下一个错误检测码。 附加到下一个单元的先前错误检测码被下一个错误检测码替换，并且发送包括附加在其上的下一个检错码的下一个单元。 以这种方式，在当前小区和先前的错误检测码上计算累积检错码。 因此，可以使用累积检错码来检测每个单独的单元中的位错误，以及检测一个或多个丢失或丢弃的单元。
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10.发明授权Method, apparatus, and system for idle state definition for power management 有权用于电源管理的空闲状态定义的方法，装置和系统公开(公告)号：US07965741B2
公开(公告)日：2011-06-21
申请号：US12511239
申请日：2009-07-29
申请人： Tim Frodsham , Naveen Cherukuri , Sanjay Darbal , David S. Dunning , Theodore Z. Schoenborn , Lakshminarayan Krishnamurty , Aaron T. Spink
发明人： Tim Frodsham , Naveen Cherukuri , Sanjay Darbal , David S. Dunning , Theodore Z. Schoenborn , Lakshminarayan Krishnamurty , Aaron T. Spink
CPC分类号： H04W52/0287 , Y02D70/00
摘要： A predetermined network packet is utilized for power reduction in either or both of a transmitter and receiver when information is not needed. Upon detection of the predetermined network packet type, various portions of the transmitter and/or receiver may be clock gated or powered down.
摘要翻译： 当不需要信息时，预定的网络分组被用于发射机和接收机中的任一个或两者中的功率降低。 在检测到预定网络分组类型时，发射机和/或接收机的各个部分可以是时钟门控或掉电。
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