利索-全球专利检索

  1. 登录
  2. 注册

搜索结果

34 条记录 (耗时 0.048 秒)

    Self-healing chip-to-chip interface
    2.
    发明授权
    Self-healing chip-to-chip interface 失效
    自愈芯片到芯片的接口

    公开(公告)号：US07362697B2

    公开(公告)日：2008-04-22

    申请号：US10339757

    申请日：2003-01-09

    申请人： Wiren Dale Becker ,  Daniel Mark Dreps ,  Frank David Ferraiolo ,  Anand Haridass ,  Robert James Reese

    发明人： Wiren Dale Becker ,  Daniel Mark Dreps ,  Frank David Ferraiolo ,  Anand Haridass ,  Robert James Reese

    IPC分类号： G01R31/08

    CPC分类号： H01L22/22 ,  H01L2924/0002 ,  H01L2924/00

    摘要： A method, apparatus, and computer instructions for managing a set of signal paths for a chip. A defective signal path within the set of signal paths for the chip is detected. Signals are re-routed through the set of signal paths such that the defective signal path is removed from the set of signal paths and sending signals using remaining data signal paths in the set of signal paths and using an extra signal path in response to detecting the defective signal path.

    摘要翻译： 一种用于管理用于芯片的一组信号路径的方法，装置和计算机指令。 检测用于芯片的信号路径集合内的有缺陷的信号路径。 信号通过一组信号路径重新路由，使得有缺陷的信号路径从信号路径集合中移除，并使用信号路径组中的剩余数据信号路径发送信号，并且响应于检测到的信号路径 有缺陷的信号路径。

    System for latching first and second data on opposite edges of a first clock and outputting both data in response to a second clock
    4.
    发明授权
    System for latching first and second data on opposite edges of a first clock and outputting both data in response to a second clock 失效
    用于在第一时钟的相对边缘上锁存第一和第二数据并响应于第二时钟输出两个数据的系统

    公开(公告)号：US06542999B1

    公开(公告)日：2003-04-01

    申请号：US09434801

    申请日：1999-11-05

    申请人： Daniel Mark Dreps ,  Kevin Charles Gower ,  Frank David Ferraiolo

    发明人： Daniel Mark Dreps ,  Kevin Charles Gower ,  Frank David Ferraiolo

    IPC分类号： G06F112

    CPC分类号： G06F5/06

    摘要： An elastic interface apparatus and method are implemented. The elastic interface includes a plurality of storage units for storing for storing a stream of data values, wherein each storage unit sequentially stores members of respective sets of data values. Each data value is stored for a predetermined number of periods of a local clock. Selection circuitry may be coupled to the storage units to select the respective data value from the data stream for storage in the corresponding storage unit. Data is sequentially output from each storage unit in synchrony with the local clock on a target cycle of the local clock.

    摘要翻译： 实现弹性接口装置和方法。 弹性接口包括用于存储数据值流的多个存储单元，其中每个存储单元顺序地存储各组数据值的成员。 每个数据值被存储在本地时钟的预定数量的周期内。 选择电路可以耦合到存储单元以从数据流中选择相应的数据值，以存储在相应的存储单元中。 与本地时钟的目标周期上的本地时钟同步地从每个存储单元顺序地输出数据。

    Method and system for data transfer
    5.
    发明授权
    Method and system for data transfer 失效
    数据传输方法和系统

    公开(公告)号：US06442223B1

    公开(公告)日：2002-08-27

    申请号：US09299716

    申请日：1999-04-26

    申请人： Daniel Mark Dreps ,  Frank David Ferraiolo ,  Kevin Charles Gower ,  Toru Kobayashi ,  Bradley David McCredie ,  Hideo Sawamoto

    发明人： Daniel Mark Dreps ,  Frank David Ferraiolo ,  Kevin Charles Gower ,  Toru Kobayashi ,  Bradley David McCredie ,  Hideo Sawamoto

    IPC分类号： H04L700

    CPC分类号： H04L25/05 ,  H04L7/0012 ,  H04L7/02 ,  H04L7/046

    摘要： A method and system for increasing speeds of transferring data in a data transfer system which includes a data source and data sink. Both the data source and data sink include clocks which are synchronized to a common clock frequency. A buffer is provided at the data sink and this buffer is utilized to received data from the data source. A control circuit is provided at the data sink and this control circuit receives a bus clock signal from the data source. An N segment dynamic shift register is provided within the data sink which includes at least two segments. A selectable shift control is provided for passing the data through an M segment subset of the N segment shift register, where M is less than N. Additionally, the length of the M segment subset is determined by the phase of a clock within the data sink at the time which the bus clock signal from the data source is received at the data sink. By selectively passing the data through an M segment subset of the N segment shift register, the data is accessible at the data sink at a controllable predetermined time.

    摘要翻译： 一种用于在包括数据源和数据宿的数据传输系统中提高传输数据速度的方法和系统。 数据源和数据宿均包含与公共时钟频率同步的时钟。 在数据接收器处提供缓冲器，并且该缓冲器用于从数据源接收数据。 在数据宿提供控制电路，该控制电路从数据源接收总线时钟信号。 N段动态移位寄存器提供在数据宿内，其包括至少两个段。 提供了可选择的移位控制，用于使数据通过N段移位寄存器的M段子集，其中M小于N.另外，M段子集的长度由数据宿内的时钟的相位确定 在数据接收器处接收到来自数据源的总线时钟信号的时间。 通过选择性地将数据通过N段移位寄存器的M段子集，可以在可控的预定时间在数据宿处访问数据。

    Elastic interface for master-slave communication
    7.
    发明授权
    Elastic interface for master-slave communication 有权
    用于主从通信的弹性接口

    公开(公告)号：US06571346B1

    公开(公告)日：2003-05-27

    申请号：US09434800

    申请日：1999-11-05

    申请人： Daniel Mark Dreps ,  Frank David Ferraiolo ,  Kevin Charles Gower ,  Bradley McCredie ,  Paul Coteus

    发明人： Daniel Mark Dreps ,  Frank David Ferraiolo ,  Kevin Charles Gower ,  Bradley McCredie ,  Paul Coteus

    IPC分类号： G06F104

    CPC分类号： G06F5/06

    摘要： A method and apparatus are disclosed for communicating between a master and slave device. A sequence of data sets and a clock signal (“Bus clock”) are sent from the master to the slave, wherein the successive sets are asserted by the master at a certain frequency, each set being asserted for a certain time interval. The data and Bus clock are received by the slave, including capturing the data by the slave, responsive to the received Bus clock. The slave generates, from the received Bus clock, a clock (“Local clock”) for clocking operations on the slave. The sequence of the received data sets is held in a sequence of latches in the slave, each set being held for a time interval that is longer than the certain time interval for which the set was asserted by the master. The data sets are read in their respective sequence from the latches, responsive to the Local clock, so that the holding of respective data sets for the relatively longer time intervals in multiple latches and the reading of the data in sequence increases allowable skew of the Local clock relative to the received Bus clock.

    摘要翻译： 公开了用于在主设备和从设备之间进行通信的方法和设备。 一系列数据组和时钟信号（“总线时钟”）从主机发送到从机，其中连续组由主机以某一频率断言，每组都被断言一段时间间隔。 数据和总线时钟由从机接收，包括响应于接收的总线时钟由从机捕获数据。 从器件从接收的总线时钟产生一个时钟（“本地时钟”），用于在从机上进行时钟操作。 所接收的数据集的序列被保持在从属序列中的锁存器序列中，每个集合被保持一段时间间隔，该时间间隔长于由主机确定该集合的特定时间间隔。 响应于本地时钟，从锁存器读取它们各自的序列中的数据集，使得在多个锁存器中相对较长的时间间隔保持相应的数据集并且依次读取数据增加本地 时钟相对于接收的总线时钟。

    Phase detector
    8.
    发明授权
    Phase detector 失效
    相位检测器

    公开(公告)号：US06762626B1

    公开(公告)日：2004-07-13

    申请号：US10422686

    申请日：2003-04-24

    申请人： Daniel Mark Dreps ,  Frank David Ferraiolo ,  Kevin Charles Gower ,  Gary Alan Peterson ,  Robert James Reese

    发明人： Daniel Mark Dreps ,  Frank David Ferraiolo ,  Kevin Charles Gower ,  Gary Alan Peterson ,  Robert James Reese

    IPC分类号： H03D900

    CPC分类号： H03D13/004

    摘要： A phase detector for use in conjunction with a delay locked loop is provided. Programmable delay elements insert an adjustable delay in a received data stream. The programmable delays stress the setup and hold times of the incoming data. Phase detector sampling logic detects the phase difference between a nominal center of the data window, and the limits on the setup (early) edge of the data value window, and the hold time limit (late time) edge of the data valid window (“guardbands”). A data signal arriving earlier than an early guardband or later than a late guardband may not be correctly sampled, and a guardband failure may be said to have occurred. A state machine detects such guardband errors and provides corrective feedback signals.

    摘要翻译： 提供了一种与延迟锁定环结合使用的相位检测器。 可编程延迟元件在接收的数据流中插入可调延迟。 可编程延迟会强制输入数据的建立和保持时间。 相位检测器采样逻辑检测数据窗口的标称中心与数据值窗口的设置（早期）边沿的限制以及数据有效窗口的保持时间限制（后期）边沿之间的相位差（“ 护卫队“）。 在早期保护带之前到达晚于后期保护带的数据信号可能未被正确采样，并且可能说已经发生了保护带故障。 状态机检测这种保护带错误并提供校正反馈信号。

    Dynamic wave-pipelined interface apparatus and methods therefor
    9.
    发明授权
    Dynamic wave-pipelined interface apparatus and methods therefor 有权
    动态波形流水线接口设备及其方法

    公开(公告)号：US06654897B1

    公开(公告)日：2003-11-25

    申请号：US09263662

    申请日：1999-03-05

    申请人： Daniel Mark Dreps ,  Frank David Ferraiolo ,  Kevin Charles Gower

    发明人： Daniel Mark Dreps ,  Frank David Ferraiolo ,  Kevin Charles Gower

    IPC分类号： G06F112

    CPC分类号： G06F13/4208 ,  H04L7/04

    摘要： An apparatus and method for a dynamic wave-pipelined interface are implemented. Data signals received from a sending circuit delayed via a programmable delay device corresponding to each signal before being latched into the receiving device. The programmable delay in each delay device is set according to an initialization procedure whereby each signal is deskewed to a latest arriving signal. Additionally, a phase of an input/output (I/O) clock controlling the latching of the data signals is adjusted so that a latching transition is substantially centered in a data valid window.

    摘要翻译： 实现了一种用于动态波形流水线接口的装置和方法。 从被发送电路接收到的数据信号在被锁存到接收装置之前经由可编程延迟装置对应于每个信号而被延迟。 根据初始化过程来设置每个延迟装置中的可编程延迟，由此每个信号被偏移到最新的到达信号。 此外，调整控制数据信号的锁存的输入/输出（I / O）时钟的相位，使得锁存转换基本上位于数据有效窗口的中心。

    Linear delay element providing linear delay steps
    10.
    发明授权
    Linear delay element providing linear delay steps 失效
    线性延迟元件提供线性延迟步骤

    公开(公告)号：US06546530B1

    公开(公告)日：2003-04-08

    申请号：US09662417

    申请日：2000-09-14

    申请人： Daniel Mark Dreps ,  Frank David Ferraiolo ,  Jing Fang Hao

    发明人： Daniel Mark Dreps ,  Frank David Ferraiolo ,  Jing Fang Hao

    IPC分类号： G06F1750

    CPC分类号： H03K5/131 ,  G01R31/3016 ,  G01R31/3191 ,  G01R31/31922 ,  H03K5/133 ,  H03K2005/00058 ,  H03K2005/00195

    摘要： A method and circuitry for linearly delaying a signal with linear delay steps. In one embodiment, circuitry in an integrated circuit for linearly delaying a signal comprises a plurality of control signals. The circuitry further comprises a fine delay element coupled to at least one of the plurality of control signals where the fine delay element comprises logic circuitry configured to provide fine adjustments to the delay of the signal. The circuitry further comprises at least one course delay element coupled to the fine delay element where the at least one course delay element is coupled to at least one of the plurality of control signals. Furthermore, the at least one course delay element comprises logic circuitry configured to provide course adjustments to the delay of the signal. The circuitry for linearly delaying a signal is configured to provide testability and programmability. The circuitry for linearly delay a signal is configured to provide linear delay steps. In another embodiment of the present invention, a test signal is coupled to the fine delay element and to the at least one course delay element. The test signal is used to detect faults at the fine delay element and at the at least one course delay element. During the functional mode of this embodiment, power is reduced by disconnecting the test path during the functional mode.

    摘要翻译： 一种线性延迟线性延迟信号的方法和电路。 在一个实施例中，用于线性延迟信号的集成电路中的电路包括多个控制信号。 电路还包括耦合到多个控制信号中的至少一个控制信号的精细延迟元件，其中精细延迟元件包括被配置为提供对信号延迟的精细调节的逻辑电路。 所述电路还包括耦合到所述精细延迟元件的至少一个线路延迟元件，其中所述至少一个线路延迟元件耦合到所述多个控制信号中的至少一个。 此外，所述至少一个路线延迟元件包括逻辑电路，其被配置为向所述信号的延迟提供路线调整。 用于线性延迟信号的电路被配置为提供可测试性和可编程性。 用于线性延迟信号的电路被配置为提供线性延迟步骤。 在本发明的另一个实施例中，测试信号耦合到精细延迟元件和至少一个线程延迟元件。 测试信号用于检测精细延迟元件和至少一个行程延迟元件的故障。 在本实施例的功能模式期间，在功能模式期间通过断开测试路径来降低功率。