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公开(公告)号：US07054374B1
公开(公告)日：2006-05-30
申请号：US09752813
申请日：2000-12-29
CPC分类号： H04L5/1423 , H04L7/0079 , H04L7/0087 , H04L7/0338
摘要： When signaling over cables or other media having significant return impedance, it is generally more efficient to use two conductors to carry two simultaneous bi-directional signals differentially, rather than utilizing unidirectional communications. Bi-directional communications increases the aggregate bandwidth of a pair of conductors. A conversion circuit converts unidirectional signaling between an edge-based receiver and a transmitter to simultaneous differential bi-directional signaling. A receiver for receiving data includes an edge processor operative to make decisions using edges of a received data stream and a communication circuit coupled to the edge processor. The communication circuit is operative to convert communications with the edge processor from a first format, such as unidirectional signaling, to a second format, such as differential bi-directional signaling.
摘要翻译： 当通过电缆或具有显着回波阻抗的其它介质发信号时，使用两个导体差分地携带两个同时的双向信号通常更有效，而不是利用单向通信。 双向通信增加了一对导体的总带宽。 转换电路将基于边缘的接收机和发射机之间的单向信令转换为同步差分双向信令。 用于接收数据的接收机包括边缘处理器，其可操作以使用接收到的数据流的边缘和耦合到边缘处理器的通信电路进行判定。 通信电路可操作以将与边缘处理器的通信从诸如单向信令的第一格式转换为诸如差分双向信令的第二格式。
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2.发明授权公开(公告)号：US07113562B1
公开(公告)日：2006-09-26
申请号：US09749270
申请日：2000-12-27
CPC分类号： H04L25/068 , H03D3/006 , H04L7/005 , H04L7/0331
摘要： Conventional receiver architectures are based on either frequency/phase tracking or oversampling. Both receiver types typically employ sensitive analog circuits, which create noise, consume power and utilize valuable space in their implementation. The invention adopts a novel approach to phase/frequency tracking that utilizes the edges or zero crossings of the input data waveform to effectively track the remote transmitter clock phase/frequency. This methodology minimizes the use of analog circuitry, thereby reducing the noise domain and the substrate space required for implementation of a tracking device.
摘要翻译： 传统的接收机架构基于频率/相位跟踪或过采样。 两种接收机类型通常采用灵敏的模拟电路，它们产生噪声，消耗功率并在其实现中利用有价值的空间。 本发明采用新颖的相位/频率跟踪方法，利用输入数据波形的边缘或过零点有效跟踪远程发射机时钟相位/频率。 该方法最大限度地减少了模拟电路的使用，从而降低了实现跟踪设备所需的噪声区域和衬底空间。
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公开(公告)号：US06917659B1
公开(公告)日：2005-07-12
申请号：US09749269
申请日：2000-12-27
CPC分类号： H04L7/0054 , H04L7/005 , H04L7/0337
摘要： A method of recovering data from a modulated data signal includes tracking a transmitted clock with a plurality of locally-generated clock phases, estimating an average phase of previously detected edges, registering a pulse edge in the received stream of data at a transition phase corresponding to one of the plurality of locally-generated clock phases, determining whether a first symbol was received multiple times consecutively prior to the registered pulse edge, and using the determination of whether the first symbol was received multiple times consecutively in a receiver decision process.
摘要翻译： 从调制数据信号恢复数据的方法包括利用多个本地生成的时钟相位跟踪传输的时钟，估计先前检测到的边沿的平均相位，在所接收的数据流中在对应于 所述多个本地生成的时钟相位中的一个，确定在所述注册的脉冲沿之前连续地多次接收到第一符号，并且使用在所述接收机决定处理中是否连续地接收到所述第一符号的确定。
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4.发明授权公开(公告)号：US07280629B2
公开(公告)日：2007-10-09
申请号：US10969737
申请日：2004-10-19
CPC分类号： H04L25/068 , H03D3/006 , H04L7/005 , H04L7/0331
摘要： Conventional receiver architectures are based on either frequency/phase tracking or oversampling. Both receiver types typically employ sensitive analog circuits, which create noise, consume power and utilize valuable space in their implementation. The invention adopts a novel approach to phase/frequency tracking that utilizes the edges or zero crossings of the input data waveform to effectively track the remote transmitter clock phase/frequency. This methodology minimizes the use of analog circuitry, thereby reducing the noise domain and the substrate space required for implementation of a tracking device.
摘要翻译： 传统的接收机架构基于频率/相位跟踪或过采样。 两种接收机类型通常采用灵敏的模拟电路，它们产生噪声，消耗功率并在其实现中利用有价值的空间。 本发明采用新颖的相位/频率跟踪方法，利用输入数据波形的边缘或过零点有效跟踪远程发射机时钟相位/频率。 该方法最大限度地减少了模拟电路的使用，从而降低了实现跟踪设备所需的噪声区域和衬底空间。
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5.发明授权Method and apparatus for a tracking data receiver compensating for deterministic jitter 有权跟踪数据接收机补偿确定性抖动的方法和装置公开(公告)号：US06765975B2
公开(公告)日：2004-07-20
申请号：US09741319
申请日：2000-12-19
IPC分类号： H04L2536
CPC分类号： H04L7/0338 , H04L7/033
摘要： A tracking data receiver which can compensate for deterministic jitter is disclosed. The device utilizes a history of past data received to determine which of multiple samples taken within a bit period to utilize. Due to deterministic jitter that can occur in data signal communication, the delay of waveform development varies with the ratio of 0's to 1's transmitted prior to the bit period being observed. The present invention exploits the predictable nature of the deterministic jitter to decide which sample to choose.
摘要翻译： 公开了可补偿确定性抖动的跟踪数据接收机。 该设备利用接收到的过去数据的历史来确定在一个位周期内采用的多个样本中的哪个采样。 由于可能发生在数据信号通信中的确定性抖动，波形发展的延迟随着观察到比特周期之前发送的0到1的比率而变化。 本发明利用确定性抖动的可预测性来决定要选择哪个样本。
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公开(公告)号：US06606360B1
公开(公告)日：2003-08-12
申请号：US09475505
申请日：1999-12-30
IPC分类号： H04L700
CPC分类号： H04L7/0338
摘要： A method and apparatus for asynchronously receiving a stream of data. The method and apparatus operate to detect edges within the stream of data and track a transmitted clock using multiple locally-generated clock phases. Moreover, the method and apparatus determine whether each edge arrives early or late relative to an expected arrival time and use the determination whether an edge arrived early or late in a receiver decision process. An exemplary embodiment of the apparatus to recover a clock from a stream of data includes an edge buffer, an edge processor, a multi-phase clock and an elastic buffer. The edge buffer receives the data stream and outputs an edge signal that indicates detection of an edge within the data stream. The edge processor is coupled to the edge buffer, determines an average phase of the detected edges and outputs a data signal and the average phase. The multi-phase clock is coupled to the edge processor, and outputs a multiple clock phases offset from each other by a predetermined amount. The elastic buffer is coupled to the edge processor and the multi-phase clock and outputs the data and the average phase.
摘要翻译： 一种用于异步接收数据流的方法和装置。 所述方法和装置用于检测数据流内的边缘并且使用多个本地生成的时钟相位来跟踪发送的时钟。 此外，该方法和装置确定每个边缘是否相对于预期到达时间早到或晚进行，并且使用确定边缘在接收机决策过程中是早到还是迟。 从数据流恢复时钟的装置的示例性实施例包括边缘缓冲器，边缘处理器，多相时钟和弹性缓冲器。 边缘缓冲器接收数据流并输出指示检测数据流内的边缘的边缘信号。 边缘处理器耦合到边缘缓冲器，确定检测到的边缘的平均相位并输出数据信号和平均相位。 多相时钟耦合到边缘处理器，并输出多个时钟相位彼此偏移预定量。 弹性缓冲器耦合到边缘处理器和多相时钟并输出数据和平均相位。
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7.发明申请公开(公告)号：US20050078782A1
公开(公告)日：2005-04-14
申请号：US10969737
申请日：2004-10-19
CPC分类号： H04L25/068 , H03D3/006 , H04L7/005 , H04L7/0331
摘要： Conventional receiver architectures are based on either frequency/phase tracking or oversampling. Both receiver types typically employ sensitive analog circuits, which create noise, consume power and utilize valuable space in their implementation. The invention adopts a novel approach to phase/frequency tracking that utilizes the edges or zero crossings of the input data waveform to effectively track the remote transmitter clock phase/frequency. This methodology minimizes the use of analog circuitry, thereby reducing the noise domain and the substrate space required for implementation of a tracking device.
摘要翻译： 传统的接收机架构基于频率/相位跟踪或过采样。 两种接收机类型通常采用灵敏的模拟电路，它们产生噪声，消耗功率并在其实现中利用有价值的空间。 本发明采用新颖的相位/频率跟踪方法，利用输入数据波形的边缘或过零点有效跟踪远程发射机时钟相位/频率。 该方法最大限度地减少了模拟电路的使用，从而降低了实现跟踪设备所需的噪声区域和衬底空间。
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公开(公告)号：US06943606B2
公开(公告)日：2005-09-13
申请号：US09891466
申请日：2001-06-27
申请人： Davied S. Dunning , Chamath Abhayagunawardhana , Ken Drottar , Richard S. Jensen , Robert Glenn
发明人： Davied S. Dunning , Chamath Abhayagunawardhana , Ken Drottar , Richard S. Jensen , Robert Glenn
CPC分类号： H03L7/0814 , H03K5/13 , H03K2005/00286
摘要： A phase interpolator interpolates between a plurality of clock phases using a plurality of switching legs coupled to a common output. Each switching leg includes a pair of differential switching transistors each having a gate and two additional terminals, one of which is coupled to said common output. The gates are coupled to respective ones of the plurality of clock phases and their complements. Tails couple the other terminals of said switching transistors to ground. Each tail made up of a plurality of transistors. A load coupling the common output to a voltage.
摘要翻译： 相位插值器使用耦合到公共输出的多个开关支路在多个时钟相位之间内插。 每个开关支路包括一对差分开关晶体管，每个具有栅极和两个附加端子，其中一个连接到所述公共输出端。 门耦合到多个时钟相位中的相应时钟相位及其补码。 尾部将所述开关晶体管的其它端子耦合到地。 每个尾部由多个晶体管组成。 将公共输出耦合到电压的负载。
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公开(公告)号：US07474714B2
公开(公告)日：2009-01-06
申请号：US10334935
申请日：2002-12-31
IPC分类号： H04L27/00
CPC分类号： H04L7/033
摘要： A receiving device within a digital electronic system includes a sampling unit, a voter block, and a local clock phase adjustment unit. The sampling unit samples an input line at three points in time at intervals of one half of a bit period. The sampling unit delivers the values obtained in the sampling process to the voter block. The voter block determines whether to deliver an up or a down vote to the local clock phase adjustment unit. The voter block communicates with the local clock phase adjustment unit via up and down control signals. The local clock phase adjustment unit determines whether the local clock phase should be adjusted, and if so, whether to advance or delay the local clock phase. If certain meta-stable conditions are observed by the voter block, the voter block will vote in one direction in order to push the system out of the meta-stable condition.
摘要翻译： 数字电子系统内的接收装置包括采样单元，选举块和本地时钟相位调整单元。 采样单元在三个时间点以一个位周期的一半的间隔对输入行进行采样。 采样单元将采样过程中获得的值传递给选举块。 选民块决定是否向本地时钟相位调整单位输出向上或向下的投票。 选举块通过上下控制信号与本地时钟相位调整单元进行通信。 本地时钟相位调整单元确定是否应调整本地时钟相位，如果是，是否提前或延迟本地时钟相位。 如果选民块观察到某些元稳定条件，则选民块将以一个方向投票，以将该制度推出元稳定状态。
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公开(公告)号：US07126986B2
公开(公告)日：2006-10-24
申请号：US10262359
申请日：2002-09-30
CPC分类号： G06F1/12 , H03L7/0814 , H03L7/089 , H03L7/093 , H04L7/0008 , H04L7/0025
摘要： A method and system for improved phase tracking in communication systems is disclosed. In one embodiment, a method, comprises identifying a slow-time varying phase drift on a link by counting long term beats; calibrating an interpolator with the phase drift; predicting a future phase drift; and updating the interpolator periodically with the future phase drift prediction.
摘要翻译： 公开了一种用于改进通信系统中的相位跟踪的方法和系统。 在一个实施例中，一种方法包括通过计数长期节拍来识别链路上的慢时变化相位漂移; 校准具有相位漂移的内插器; 预测未来相位漂移; 以及随着未来的相位漂移预测周期性地更新内插器。
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