公开(公告)号：USRE34843E

公开(公告)日：1995-01-31

申请号：US288029

申请日：1988-12-20

Applicant: Hugo S. Ferguson

Inventor： Hugo S. Ferguson

IPC: G01R13/04 ,  G01R13/28 ,  G01R13/32 ,  G01R13/34 ,  G06F3/05 ,  G06F3/06

CPC classification number: G01R13/32 ,  G01R13/04 ,  G01R13/28 ,  G01R13/345

Abstract: A multi-channel electronic waveform recorder, for storing waveform data and time of occurrence information, i.e., a "time-tag", for each stored value of an input waveform, is disclosed. Specifically, each channel of the waveform recorder compares a previously stored value of a corresponding input signal to a current value .Iadd.of that signal.Iaddend., and .[.stores.]. .Iadd.is able to store .Iaddend.the current value whenever the difference between the input signal and the previously stored value is a predetermined amount. .Iadd.Each or any selected sub-set of all the channels, through an appropriate switch setting, can determine points in time when, in response to the difference occurring for that channel, all the channels will simultaneously store the current value of these respective input signals. .Iaddend.

Abstract translation: 公开了一种多通道电子波形记录仪，用于存储波形数据和发生时间信息，即“时间标签”，用于输入波形的每个存储值。 具体地，波形记录器的每个通道将相应输入信号的先前存储的值与该信号的当前值进行比较，并且每当输入信号和先前存储的值之间的差值为 预定量。 通过适当的开关设置，所有通道的每个或任何选定的子集可以确定当响应于该通道发生的差异时所有通道将同时存储这些相应输入信号的当前值的时间点。

公开(公告)号：US5373293A

公开(公告)日：1994-12-13

申请号：US876093

申请日：1992-04-30

Applicant: Yasushi Hirata

Inventor： Yasushi Hirata

IPC: G06F3/05 ,  H03M1/08 ,  H03M1/12 ,  H03M1/06

CPC classification number: H03M1/08 ,  H03M1/12

Abstract: In mixed analog/digital integrated circuit constructed by an analog unit, typically an A/D converter, which processes an analog signal and converts it into a digital signal, a digital unit for processing the digital signal, and a clock signal generator for supplying operating clock signals to the analog unit and the digital unit, a clock signal stop circuit for stopping an operating clock signal supplied to the digital unit during an operation of the analog unit is provided, thus adverse effect on the analog unit by the digital noise generated by the digital unit is eliminated.

Abstract translation: 在由模拟单元（通常是A / D转换器）构成的混合模拟/数字集成电路中，模拟单元处理模拟信号并将其转换成数字信号，用于处理数字信号的数字单元和用于提供操作的时钟信号发生器 提供到模拟单元和数字单元的时钟信号，用于在模拟单元的操作期间停止提供给数字单元的操作时钟信号的时钟信号停止电路，由此通过由模拟单元产生的数字噪声对模拟单元产生不利影响 数字单元被消除。

公开(公告)号：US5327129A

公开(公告)日：1994-07-05

申请号：US87943

申请日：1993-07-06

Applicant: Eric G. Soenen ,  Randall L. Geiger

Inventor： Eric G. Soenen ,  Randall L. Geiger

IPC: G06F3/05 ,  H03H15/00 ,  H03H17/02 ,  H03H17/04 ,  H03H21/00 ,  H03M1/10 ,  H03M1/12 ,  H03M1/16 ,  H04B3/04

CPC classification number: H03M1/1061 ,  H03M1/168

Abstract: A method and apparatus for a system physically realizing a transfer function and having improved accuracy and fast calibration is described, comprising a plurality of stages configured in a serial fashion, each stage having a transfer function realized with fixed and adjustable elements. Control logic for selectively reconfiguring said stages, operable for coupling any one of said stages to a reference signal and for further coupling said one of said stages to the remaining ones of said stages in a serial fashion is added; control logic for selectively causing said stages to transmit at their output responses to an input which enable measurement of individual components within said stages is included; and control logic for updating the adjustable elements within each stage is described. A calibration technique is disclosed wherein the system is reconfigured to allow any one of said stages to be configured as the first stage in a chain made up of all of said stages, serially coupled, the first stage outputting signals indicative of the value of components within it in response to selective excitation by the reference signal, the remaining stages capturing said outputted signals and storing the result as a measurement.The calibration process continues until the adjustable elements within each stage have been updated. Additional cycles may be performed for increased accuracy. An additional preferred embodiment of an analog-to-digital converter implemented using the accuracy bootstrapping invention is disclosed. Other embodiments are also disclosed.

Abstract translation: 描述了一种用于物理实现传递函数并具有改进的精度和快速校准的系统的方法和装置，包括以串联方式配置的多个级，每个级具有通过固定和可调元件实现的传递函数。 控制逻辑用于选择性地重新配置所述级，可操作用于将所述级中的任何一个耦合到参考信号，并且用于以串行方式进一步将所述级中的所述级与所述级中的剩余级耦合; 控制逻辑用于选择性地使所述级在其输出响应处发送到能够测量所述级内的各个组件的输入; 并描述用于更新每个阶段内的可调节元件的控制逻辑。 公开了一种校准技术，其中系统被重新配置为允许所述级中的任何一个被配置为由所有所述级组成的链中的第一级，串行耦合，第一级输出指示组件内部的值的信号 响应于参考信号的选择性激励，其余级捕获所述输出信号并将结果存储为测量值。 校准过程继续进行，直到每个阶段内的可调节元件都被更新。 可以执行额外的循环以提高精度。 公开了使用精度自举发明实现的模数转换器的另一优选实施例。 还公开了其他实施例。

公开(公告)号：US5301140A

公开(公告)日：1994-04-05

申请号：US997984

申请日：1992-12-28

Applicant: Nobuskue Abe

Inventor： Nobuskue Abe

IPC: G06F3/05 ,  G01R31/3167 ,  G01R35/00 ,  H03M1/08 ,  H03M1/12 ,  G06F7/50

CPC classification number: H03M1/129 ,  G01R31/3167 ,  G01R35/00

Abstract: The result of an analog to digital conversion is stored in a first storage unit, the contents of the first storage unit are transferred to a second storage unit, and the contents of these storage units are compared by an arithmetic unit to determine whether the result of the analog to digital conversion increases or decreases over time.

Abstract translation: 模拟数字转换的结果存储在第一存储单元中，第一存储单元的内容被传送到第二存储单元，并且这些存储单元的内容由算术单元进行比较，以确定是否将结果 模数转换随时间增加或减少。

公开(公告)号：US5225834A

公开(公告)日：1993-07-06

申请号：US801359

申请日：1991-12-02

Applicant: Kiyoshi Imai ,  Toshiaki Tsuji ,  Taku Takada ,  Seiichi Taguchi

Inventor： Kiyoshi Imai ,  Toshiaki Tsuji ,  Taku Takada ,  Seiichi Taguchi

IPC: G06F3/05 ,  G01R31/3167 ,  G01R31/3185 ,  H03M1/12

CPC classification number: G01R31/3167 ,  G01R31/318536

Abstract: A semiconductor integrated circuit having a test circuit built therein is disclosed which consists of an A/D converter to be connected to a peripheral circuit, a digital circuit connected to the A/D converter, a digital signal switching device for selectively connecting to the output of the A/D converter and that of the digital circuit, and a boundary scan output circuit connected to the output of the digital signal switching device, wherein the digital signal switching device connects the A/D converter to the boundary scan output circuit in a normal mode, while the signal fetched in the boundary scan output circuit is outputted therefrom in test mode. Semiconductor integrated circuits having an analog circuit built therein and an analog integrated circuit in which a test circuit is built-in are also disclosed.

公开(公告)号：US5172334A

公开(公告)日：1992-12-15

申请号：US671325

申请日：1991-03-19

Applicant: Klaus Hienerwadel

Inventor： Klaus Hienerwadel

IPC: G06F3/05 ,  G06F17/15 ,  G10L15/02

CPC classification number: G06F17/15

Abstract: A circuit arrangement for defining the positions of extrema of a correlation function includes a memory (1), an address control unit (3) and a correlator (2). The elaborate computations for defining correlation functions can be reduced by the circuit arrangement described. The correlation function is an example. Two functions are present in digital form. Their sampling values are stored in the addressable memory (1). The address control unit (3) generates addresses by which the functions stored in the memory (1) are read in a sub-sampled manner. With these sub-sampled functions the extrema and their positions are defined in a first step by the correlator (2) and the address control unit (3). Proximate to an extremum thus defined the variation of the correlation functions is examined more precisely in this proximity in a smaller sub-sampling ratio and the extremum in this proximity is redefined. This process can be repeated with an increasingly smaller sub-sampling ratio.

Abstract translation: 用于定义相关函数的极值位置的电路​​装置包括存储器（1），地址控制单元（3）和相关器（2）。 通过所描述的电路布置可以减少用于定义相关函数的精细计算。 相关函数是一个例子。 两种功能以数字形式存在。 它们的采样值存储在可寻址存储器（1）中。 地址控制单元（3）产生以子采样方式读取存储器（1）中存储的功能的地址。 利用这些子采样函数，相关器（2）和地址控制单元（3）在第一步中定义极值及其位置。 近似于这样定义的极值，在较小的子采样比例中，在这种接近程度下更精确地检查相关函数的变化，并重新定义了该近似值的极值。 该过程可以以越来越小的子采样比重复。

公开(公告)号：US5113498A

公开(公告)日：1992-05-12

申请号：US533200

申请日：1990-06-04

Applicant: Shabtai Evan ,  Wendell B. Sander

Inventor： Shabtai Evan ,  Wendell B. Sander

IPC: G06F1/04 ,  G06F3/05 ,  G08C15/00 ,  H02J13/00 ,  H04L12/28

CPC classification number: H04L12/282 ,  G06F1/04 ,  G06F3/05 ,  G08C15/00 ,  H02J13/0089 ,  H04L12/2803 ,  H04L12/2838 ,  H04L2012/2841 ,  H04L2012/2843 ,  Y02B70/325 ,  Y02E60/7815 ,  Y04S20/228 ,  Y04S40/121

Abstract: A network for providing sensing, communications and control is described. A plurality of intelligent cells each of which comprises an integrated circuit having a processor and input/output section are coupled to the network. Each of the programmable cells receives when manufactured a unique identification number (48 bits) which remains permanently within the cell. The cells can be coupled to different media such as power lines, twisted, pair, radio frequency, infrared ultrasonic, optical coaxial, etc., to form a network. The preferred embodiment of the cell includes a multiprocessor and multiple I/O subsections where any of the processors can communicate with any of the I/O subsections. This permits the continual execution of a program without potential interruptions caused by interfacing with the I/O section. The I/O section includes programmable A-to-D and programmable D-to-A converters as well as other circuits for other modes of operation.

Abstract translation: 描述了用于提供感测，通信和控制的网络。 多个智能电池，每个智能电池均包括具有处理器和输入/输出部分的集成电路耦合到网络。 每个可编程单元在制造一个永久保持在单元内的唯一标识号（48位）时接收。 电池可以耦合到诸如电力线，扭曲，对，射频，红外超声波，光学同轴等不同介质，以形成网络。 小区的优选实施例包括多处理器和多个I / O子部分，其中任何处理器可以与任何I / O子部分通信。 这允许连续执行程序，而不会因与I / O部分的接口而导致中断。 I / O部分包括可编程的A到D和可编程的D到A转换器以及其他操作模式的电路。

公开(公告)号：US5087915A

公开(公告)日：1992-02-11

申请号：US459531

申请日：1990-01-02

Applicant: Tatsuro Toya

Inventor： Tatsuro Toya

IPC: H03M1/12 ,  G06F3/05

CPC classification number: G06F3/05

Abstract: A single-chip microcomputer is comprised of an analog to digital converter, a first external terminal which receives an analog signal which is to be converted by the analog to digital converter, and a second external terminal for receiving a signal indicating an operating condition of the analog to digital converter.

Abstract translation: 单片微型计算机由模拟数字转换器构成，第一外部端子接收要由模数转换器转换的模拟信号，第二外部端子用于接收指示信号的操作状态的信号 模数转换器。

公开(公告)号：US5047772A

公开(公告)日：1991-09-10

申请号：US533263

申请日：1990-06-04

Applicant: David B. Ribner

Inventor： David B. Ribner

IPC: G06F3/05 ,  H03M1/10 ,  H03M1/16 ,  H03M1/44

CPC classification number: H03M1/1061 ,  H03M1/1042 ,  H03M1/167

Abstract: A general architecture to correct conversion errors of a multi-stage, pipelined subranging analog-to-digital (A/D) converter includes cascaded stages, each stage generating a binary conversion signal representing the nearest quantized level below that of the analog input signal and a residual analog signal applied to the next conversion stage. The binary conversion signal from each stage addresses individual or common look-up tables providing a compensated binary signal selected to compensate for nonidealities of the A/D converter components. The compensated binary signals from the look-up tables provide a corrected output signal when summed together. A simple method of calibration for the A/D converter makes use of a least-mean-squared adaptation algorithm. The A/D converter accommodates practical circuit nonidealities such as component mismatching, gain error and voltage offsets, and handles high levels of amplifier nonlinearity. The architecture is applicable to any subranging converter with arbitrary numbers of stages and bits per stage.

公开(公告)号：US5043911A

公开(公告)日：1991-08-27

申请号：US455271

申请日：1989-12-22

Applicant: Abdul Rashid

Inventor： Abdul Rashid

IPC: G05B19/042 ,  G06F3/05

CPC classification number: G06F3/05 ,  G05B19/0423 ,  G05B2219/21008 ,  G05B2219/25431 ,  G05B2219/25432 ,  G05B2219/25474 ,  Y02B70/3241 ,  Y04S20/227

Abstract: A "reversible master/slave" handshaking protocol is disclosed for addressing the problem of interfacing a multiplexing analog-to-digital (A/D) converter, having a first operating rate, to a microprocessor, having a second operating rate. In the specific embodiment of a generator control unit (GCU) for an electrical power generating system, an analog multiplexer (124), an A/D converter (126), and a dual-port RAM (130) are controlled by an A/D controller (134) to provide data words to a voltage regulator processor (92). If a fast A/D converter is used, then the A/D controlling system will multiplex and convert samples from all of the analog input signals, load the RAM, and wait for the processor to read the RAM. If the A/D conversion rate is slow, the A/D controller will continuously sample all the multiplexed channels, while the processor waits for the appropriate channel information to be loaded into the RAM. In this manner, data acquisition can be perform utilizing A/D converters having various conversion rates, multiplexers having additional channels, or microprocessors having numerous feedback control loops.

Abstract translation: 公开了一种“可逆主/从”握手协议，用于解决具有第一工作速率的具有第二工作速率的具有第一工作速率的多路复用模数转换器（A / D）转换器连接到微处理器的问题。 在用于发电系统的发电机控制单元（GCU）的具体实施例中，模拟多路复用器（124），A / D转换器（126）和双端口RAM（130）由A / D控制器（134），用于向电压调节器处理器（92）提供数据字。 如果使用快速A / D转换器，则A / D控制系统将对所有模拟输入信号进行多路复用和转换，加载RAM，并等待处理器读取RAM。 如果A / D转换速率较慢，则A / D控制器将连续对所有多路复用通道进行采样，同时处理器等待相应的通道信息加载到RAM中。 以这种方式，可以利用具有各种转换速率的A / D转换器，具有附加通道的多路复用器或具有许多反馈控制回路的微处理器来执行数据采集。