Monitoring transitions of a circuit

    公开(公告)号:US11755342B2

    公开(公告)日:2023-09-12

    申请号:US17123407

    申请日:2020-12-16

    CPC classification number: G06F9/4498 G05B19/045 G06F8/34

    Abstract: A circuit includes a guard trigger circuit that includes a first input node adapted to be coupled to a first state signal, a second input node adapted to be coupled to a second state signal and an output node. The circuit also includes a reset synchronizer circuit that includes an input node coupled to the output node of the guard trigger circuit, a clock node adapted to be coupled to a clock signal and an output node. The circuit further includes a timeout circuit including an input node coupled to the output node of the reset synchronizer circuit, a clock node adapted to be coupled to the clock signal and an output node. The circuit still further includes a reset requestor circuit that includes a first input node coupled to the output node of the guard trigger circuit, a second node coupled to the output node of the timeout circuit.

    Efficient error reporting in a link interface

    公开(公告)号:US11734105B2

    公开(公告)日:2023-08-22

    申请号:US16921316

    申请日:2020-07-06

    Inventor: Kelvin Wong

    Abstract: A link interface is provided of a communication protocol using idle flow control digits (flits) to maintain link continuity. The link interface includes: a physical layer of the communication protocol configured to transmit and receive flits via a link, wherein the communication protocol provides for idle flits of first and second sizes for maintaining link continuity, the first size being smaller than the second size; and a data link layer configured to transmit and receive flits to/from the physical layer. The data link layer is configured to remove idle flits of the first size received from the physical layer and to report cyclic redundancy check errors of filtered first sized idle flits in a correct order in relation to other flits.

    MEMORY DEVICE, METHOD FOR CONTROLLING MEMORY DEVICE AND MEMORY SYSTEM

    公开(公告)号:US20230244615A1

    公开(公告)日:2023-08-03

    申请号:US18089515

    申请日:2022-12-27

    CPC classification number: G06F13/1668 G06F13/1642 G06F9/4498

    Abstract: A memory device, a method for controlling the memory device, and a memory system are provided. The memory device includes a memory array comprising a plurality of memory planes, and a peripheral circuit configured to control the plurality of memory planes to perform asynchronous operations. The peripheral circuit comprises a plurality of state machines connected to a memory interface of the memory device. Each state machine is configured to associated with one or more assigned memory planes of the plurality of memory planes. Each state machine is further configure to receive, from the memory interface in parallel with other state machines, a corresponding sequence of control commands of the one or more assigned memory planes; and independently process the corresponding sequence of control commands to obtain control information of the one or more assigned memory planes.

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