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公开(公告)号：US20130070828A1
公开(公告)日：2013-03-21
申请号：US13303268
申请日：2011-11-23
CPC分类号： H04L25/067 , H04L25/03057 , H04L25/03318 , H04L25/061 , H04L27/22 , H04L27/2331 , H04L2025/03407
摘要： A high-sensitivity receiver may be made by using multiple demodulators to demodulate a given signal. For example, the receiver may use a first demodulator to demodulate an input signal into a first sequence of soft bits and a second demodulator to demodulate the same input signal into a second sequence of soft bits. The two sequences of soft bits may then be compared and combined to create a sequence of hard bits. For example, in some embodiments, a soft bit combiner may combine the two sequences of soft bits into a third sequence of soft bits, which may then be input into a decoder to produce the final decoded hard bits. The secondary demodulator may be less complex, less expensive, demand less power, and/or require fewer computational resources when operating, than the first demodulator.
摘要翻译： 可以通过使用多个解调器来解调给定信号来制造高灵敏度接收机。 例如，接收机可以使用第一解调器将输入信号解调为第一软比特序列和第二解调器，以将相同的输入信号解调为第二个软比特序列。 然后可以比较和组合两个软比特序列以产生一个硬比特序列。 例如，在一些实施例中，软比特组合器可以将两个软比特序列组合成第三个软比特序列，然后将其输入解码器以产生最终解码的硬比特。 与第一解调器相比，次级解调器可能不那么复杂，较便宜，需要较少功率，和/或需要较少的运算资源。
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公开(公告)号：US06937871B2
公开(公告)日：2005-08-30
申请号：US10140500
申请日：2002-05-07
申请人： Burkhard Dick
发明人： Burkhard Dick
CPC分类号： H03D3/06
摘要： The invention relates to an anti-demodulator circuit which is fundamentally built up in the same way as a demodulator circuit but, instead of a bandpass filter as generally used in a demodulator, comprises a notch filter which receives an input signal comprising a useful signal and an interference signal, and generates a filtered signal. The notch filter has a center frequency which approximately corresponds to the frequency of the input signal so as to suppress at least a part of the useful signal. The anti-demodulator circuit further comprises a mixer circuit which receives the filtered signal and a phase-shifted input signal and supplies a demodulated output signal which substantially corresponds to the interference signal.The invention can be particularly used in connection with a filtering device for suppressing interference signals based on adjacent channel disturbances in FM radios, in which the bandwidth of the filtering device is controlled in dependence upon the output signal of the anti-demodulator circuit.
摘要翻译： 本发明涉及一种反解调器电路，其基本上以与解调器电路相同的方式构成，但代替通常在解调器中使用的带通滤波器，包括陷波滤波器，其接收包括有用信号的输入信号和 干扰信号，并产生滤波信号。 陷波滤波器具有大约对应于输入信号的频率的中心频率，以便抑制有用信号的至少一部分。 反解调器电路还包括混合电路，其接收经滤波的信号和相移输入信号，并提供基本上对应于干扰信号的解调输出信号。 本发明可以特别用于根据FM无线电设备中的相邻信道干扰抑制干扰信号的滤波装置，其中根据反解调器电路的输出信号控制滤波装置的带宽。
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53.发明授权Linearized integrated FM demodulator using a plurality of cascaded all-pass filters or a bessel filter 失效使用多个级联全通滤波器或贝塞尔滤波器的线性化集成FM解调器
公开(公告)号：US6137353A
公开(公告)日：2000-10-24
申请号：US107184
申请日：1998-06-29
申请人： Peter Stroet , Rishi Mohindra
发明人： Peter Stroet , Rishi Mohindra
CPC分类号： H03D3/02
摘要： An approach for demodulating a frequency-modulated signal involves processing a frequency-modulated signal with a phase shifter network to provide a demodulated signal that has a relatively constant amplitude around the center frequency of the frequency-modulated signal and that exhibits a relatively linear phase change over an operational frequency range. Embodiments of the invention include a phase shifter network, using N number of cascaded all-pass filters, that receives as an input a limited amplitude signal and outputs a phase-shifted limited amplitude signal that is mixed with the limited amplitude signal. The phase shifter network may also comprise a low-pass bessel filter.
摘要翻译： 用于解调频率调制信号的方法涉及用移相器网络处理频率调制信号，以提供在调频信号的中心频率周围具有相对恒定振幅的解调信号，并且显示相对线性的相位变化 超过工作频率范围。 本发明的实施例包括使用N个级联全通滤波器的移相器网络，其接收有限振幅信号作为输入，并输出与限幅振幅信号混合的相移限幅振幅信号。 移相器网络还可以包括低通贝塞尔滤波器。
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公开(公告)号：US5751188A
公开(公告)日：1998-05-12
申请号：US763002
申请日：1996-12-10
申请人： Herve Guegnaud , Michel Robbe
发明人： Herve Guegnaud , Michel Robbe
CPC分类号： H03D3/06 , H03D7/145 , H03D7/1458 , H03D7/1483
摘要： In order to process an input signal exhibiting a frequency modulation about an intermediate frequency, the demodulator includes a first mixer for producing a first signal exhibiting the frequency modulation about a transposition frequency lower than the intermediate frequency; a switched-capacitor phase-shifter receiving the first signal so as to produce a second signal exhibiting, with respect to the first signal, a phase-shift varying substantially linearly with frequency about the transposition frequency; two substantially identical low-pass filters receiving the second signal and the first signal respectively; and a second mixer for mixing the signals produced by the first and second low-pass filters, in order to deliver a baseband output signal.
摘要翻译： 为了处理呈现关于中频的频率调制的输入信号，解调器包括第一混频器，用于产生表现出低于中频的转置频率的频率调制的第一信号; 开关电容器移相器接收第一信号，以产生相对于第一信号表现出相对于基于转置频率的频率基本上线性地变化的相移的第二信号; 两个基本相同的低通滤波器分别接收第二信号和第一信号; 以及用于混合由第一和第二低通滤波器产生的信号的第二混频器，以便传送基带输出信号。
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公开(公告)号：US5414385A
公开(公告)日：1995-05-09
申请号：US199681
申请日：1994-02-22
IPC分类号： H03D3/06
CPC分类号： H03D3/06
摘要： A dual mode quadrature detector (15) uses the same components for both narrow band and wide band operation and provides an output amplitude which is independent of the mode of operation selected. A multiplier (32) provides a demodulated output signal (16) which is responsive to the phase difference between a signal (14) at one input (32A) and a phase shifted version of the signal at the other input (32B). A capacitor (30) and a phase shifting circuit (31) provide the phase shifted version of the signal. The phase shifting circuit (31) is responsive to a mode control signal (24) for determining the phase shift which is provided. The phase shift at the maximum frequency deviation of the narrow band signal is the same as the phase shaft at the maximum deviation of the wide band signal so that the output amplitude from the detector (15) is the same for both narrow band and wide band operation. The phase shift provided is controlled by varying the quality factor (Q) of the phase shifting circuit (31). This is achieved by controlling the amount of resistance placed in parallel with a tuned circuit (33, 34) in the phase shifting circuit (31). A higher Q is obtained by using a higher resistance, and a lower Q is obtained by using a lower resistance.
摘要翻译： 双模式正交检测器（15）对窄带和宽带操作使用相同的组件，并提供与所选择的操作模式无关的输出幅度。 乘法器（32）提供响应于一个输入端（32A）处的信号（14）与另一输入端（32B）处的信号的相移版本之间的相位差的解调输出信号（16）。 电容器（30）和移相电路（31）提供信号的相移版本。 移相电路（31）响应用于确定提供的相移的模式控制信号（24）。 窄带信号的最大频率偏移处的相移与宽带信号的最大偏差处的相位轴相同，使得来自检测器（15）的输出振幅对于窄带和宽带都是相同的 操作。 提供的相移通过改变移相电路（31）的质量因子（Q）来控制。 这通过控制与移相电路（31）中的调谐电路（33,34）并联放置的电阻量来实现。 通过使用较高的电阻获得较高的Q，并且通过使用较低的电阻获得较低的Q。
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56.发明授权
公开(公告)号：US5414383A
公开(公告)日：1995-05-09
申请号：US202139
申请日：1994-02-24
申请人： Anthony R. Cusdin , Paul A. Moore
发明人： Anthony R. Cusdin , Paul A. Moore
CPC分类号： H03D3/007 , H03D7/1408 , H03D7/1433 , H03D7/1458 , H03D7/1491 , H03D7/165 , H03D2200/0019 , H03D2200/0033
摘要： A four quadrant multiplier circuit having a high dynamic range and capable of operating at low voltages includes a dual transconductance amplifier circuit (TAC) consisting of NPN transistors (20 to 23 and 64 to 67), coupled to a first input port (36), first and second folded Darlington circuits (57,58), and a resistive element (78). Each Darlington circuit includes first and second NPN transistors (68,70 and 69,71) whose emitter-collector paths are connected in series and a third PNP transistor (72,73) having its emitter-collector path connected between the collector of the first transistor (68,69) and the base electrode of the second transistor (70,71). The emitter-collector junction (76,77) of the first and second transistors (68,70 and 69,71) is connected to the base electrode of the third transistor (72,73). The resistive element (78) is connected between the base electrodes of the third transistors (72,73). A second input port (56) is connected to the base electrodes of the first transistors (68,69). The emitter currents of the dual transconductance amplifier are supplied by way of current mirror circuits (80,81) from the emitter currents of the second transistors (70,71). The transconductance amplifier circuit (TAC) may be of any suitable type which has its transconductance linearly proportional to its emitter currents. In a refinement of the circuit, the current-to-voltage converter function of the current mirrors is carried out by the second transistors (70,71) and the transistors (82,83) of the current mirror circuits (80,81) are omitted.
摘要翻译： 具有高动态范围且能够在低电压下操作的四象限乘法器电路包括：耦合到第一输入端口（36）的由NPN晶体管（20至23和64至67）组成的双跨导放大器电路（TAC） 第一和第二折叠达林顿电路（57,58）和电阻元件（78）。 每个达林顿电路包括其发射极 - 集电极路径串联连接的第一和第二NPN晶体管（68,70和69,71）和第三PNP晶体管（72,73），其发射极 - 集电极路径连接在第一 晶体管（68,69）和第二晶体管（70,71）的基极。 第一和第二晶体管（68,70和69,71）的发射极 - 集电极结（76,77）连接到第三晶体管（72,73）的基极。 电阻元件（78）连接在第三晶体管（72,73）的基极之间。 第二输入端口（56）连接到第一晶体管（68,69）的基极。 双重跨导放大器的发射极电流通过来自第二晶体管（70,71）的发射极电流的电流镜电路（80,81）提供。 跨导放大器电路（TAC）可以是任何合适的类型，其跨导与其发射极电流成线性比例。 在电路的改进中，电流镜的电流 - 电压转换器功能由第二晶体管（70,71）和电流镜电路（80,81）的晶体管（82,83） 省略
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公开(公告)号：US5115409A
公开(公告)日：1992-05-19
申请号：US393607
申请日：1989-08-14
申请人： Richard Stepp
发明人： Richard Stepp
摘要： A four-quadrant multiplier based on a Gilbert cell is utilized to multiply several signals by a similar signal. The transistors in two pairs of coupled differential amplifiers of one input terminal of the inner multiplier that is activated like a Gilbert cell by way of a diode-and-transistor section have several emitters. Each pair of emitters in the right and the left branch of the miltiplier can be oppositely activated by way of a source of variable current or by way of a series of a transistor and a source of current. To process square-wave signals, the source of variable current is a source that can be engaged and disengaged by I.sup.2 L gates.
摘要翻译： 利用基于吉尔伯特单元的四象限乘法器，通过相似的信号来乘以几个信号。 内部乘法器的一个输入端子的两对耦合差分放大器中的晶体管像吉尔伯特单元一样通过二极管和晶体管部分被激活，具有几个发射极。 可以通过可变电流源或通过一系列晶体管和电流源来相反地激活多个反射器的右侧和左侧分支中的每对发射极。 为了处理方波信号，可变电流源是可以通过I2L门接合和分离的源。
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公开(公告)号：US4926133A
公开(公告)日：1990-05-15
申请号：US274263
申请日：1988-11-21
申请人： Takashi Koga
发明人： Takashi Koga
IPC分类号： H03D3/00 , H03D3/06 , H03D3/20 , H03K5/1532
CPC分类号： H03D3/20 , H03D2200/0039
摘要： An FM signal demodulator for converting the frequency of an input signal to a corresponding voltage. The demodulator includes a delay circuit responsive to the input signal for delaying the phase of the input signal by a fixed time, an exclusive-OR gate responsive to the input signal and the delayed phase signal from the delay circuit for outputting a pulse signal having a duration corresponding to the fixed time and an LPF responsive to the pulse signal for generating an output signal having a level which changes in response to changes in the frequency of the input signal.
摘要翻译： FM信号解调器，用于将输入信号的频率转换成相应的电压。 解调器包括响应于输入信号的延迟电路，用于将输入信号的相位延迟固定时间，响应于输入信号的异或门和来自延迟电路的延迟相位信号，用于输出具有 对应于固定时间的持续时间和响应于脉冲信号的LPF，用于产生具有响应于输入信号的频率变化而改变的电平的输出信号。
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公开(公告)号：US4926132A
公开(公告)日：1990-05-15
申请号：US399792
申请日：1989-08-28
申请人： William E. Main
发明人： William E. Main
摘要： An FM detection circuit utilizes a first multiplier and phase shift circuit to demodulate an FM signal. The output signal also contains harmonic distortion as a result of the demodulation process. A gain control circuit is included to provide a first gain control signal to the first multiplier which adjusts the magnitude of the output signal of the FM detection circuit in such a manner as to substantially eliminate the harmonic distortion. The gain control circuit uses a second multiplier to generate an output signal proportional to the square of the output signal of the phase shift circuit which is then compared to a constant current to produce an error signal proportional to the harmonic distortion. The error signal controls the magnitude of the first gain control signal such that the output signal of the FM detection circuit is proportional to the deviation of the FM signal from its center frequency.
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60.发明授权Temperature compensation circuit for a delay circuit utilized in an FM detector 失效用于FM检测器中的延迟电路的温度补偿电路
公开(公告)号：US4789976A
公开(公告)日：1988-12-06
申请号：US30159
申请日：1987-03-25
申请人： Masakazu Fujishima
发明人： Masakazu Fujishima
IPC分类号： G11B7/005 , G11B7/09 , G11B20/00 , G11B20/10 , H03D3/06 , H03D3/18 , H03K5/00 , H03K5/13 , H03K5/133 , H03K5/134 , H03K9/06 , H03K19/003 , H04N5/922 , H04N9/802 , H04N9/88 , G11B7/00
CPC分类号： G11B20/10009 , G11B20/00007 , G11B7/005 , G11B7/0946 , H03D3/18 , H03K19/00323 , H03K19/00369 , H03K5/133 , H04N9/802 , H04N9/88 , H03K2005/00097 , H03K2005/00104 , H03K2005/00195
摘要： A circuit for compensating change in delay time of a delay circuit due to variation in temperature employs, as a phase shifter of a pulse FM detection circuit, a delay circuit whose delay time is subject to change due to variation in temperature and can be controlled in response to a control signal. A dc component in an output of this pulse FM detection circuit is compared with a preset reference value and a resulting comparison output is used for controlling the delay time of the delay circuit and thereby compensating the temperature characteristic of the delay time. In a device using plural delay circuits, these delay circuits can be disposed on the same substrate and the delay times of these delay circuits can be controlled by the same comparison output. Since a signal which is handled by a delay circuit is utilized for the temperature compensation, an accurate temperature compensation can be realized with a simple circuit construction.
摘要翻译： 用于补偿由于温度变化引起的延迟电路的延迟时间变化的电路，作为脉冲FM检测电路的移相器，采用延迟电路，其延迟时间由于温度变化而变化，并且可以控制在 对控制信号的响应。 将该脉冲FM检测电路的输出中的直流分量与预先设定的基准值进行比较，得到的比较输出用于控制延迟电路的延迟时间，从而补偿延迟时间的温度特性。 在使用多个延迟电路的装置中，这些延迟电路可以设置在相同的基板上，并且可以通过相同的比较输出来控制这些延迟电路的延迟时间。 由于由延迟电路处理的信号用于温度补偿，所以可以用简单的电路结构实现精确的温度补偿。
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