公开(公告)号：US4068180A

公开(公告)日：1978-01-10

申请号：US734784

申请日：1976-10-22

申请人： William B. Nelligan

发明人： William B. Nelligan

IPC分类号： G01R23/00 ,  G01R23/15 ,  H03K5/19 ,  H03K5/153 ,  H03K5/18

CPC分类号： G01R23/15 ,  G01R23/005 ,  H03K5/19

摘要： Methods and apparatus are disclosed for selecting, among input signals, those which are time-spaced from each other by more than a predetermined time interval. Clock pulses are continuously applied to a pulse counter, and a predetermined count signal is produced each time the counter reaches a predetermined count. The counter is reset upon occurrence of either an input signal or a predetermined count signal. The order of occurrence of the input signals and of the predetermined count signals is memorized, and a validation signal is produced for each input signal which is directly preceded and followed by a predetermined count signal. Signals distorted by pile-up effect can thus be rejected.

摘要翻译： 公开了用于在输入信号中选择彼此间隔多于预定时间间隔的方法和装置。 时钟脉冲被连续施加到脉冲计数器，并且每当计数器达到预定计数时产生预定的计数信号。 在发生输入信号或预定的计数信号时，计数器被复位。 存储输入信号和预定计数信号的发生顺序，并且对于直接在预定计数信号之前和之后的每个输入信号产生有效信号。 因此，堆积效应扭曲的信号可以被拒绝。

公开(公告)号：US4060737A

公开(公告)日：1977-11-29

申请号：US687726

申请日：1976-05-19

申请人： William Milton Gosney

发明人： William Milton Gosney

IPC分类号： G11C19/28 ,  H03K3/356 ,  H03K5/18 ,  H01L29/78 ,  H03K3/286 ,  H03K3/353

CPC分类号： G11C19/28 ,  G11C19/285 ,  H03K3/35606 ,  H03K3/356078 ,  H03K3/356095

摘要： Disclosed are charge coupled device shift registers having an improved regenerative charge detector. The charge detector consists of first and second non-clocked inverter stages, gating means for coupling the input of the first inverter stage to the output of the second inverter stage in response to a first clock signal, connecting means for connecting the input of the second inverter stage to the output of the first inverter stage, and feedback means for connecting the input and output of the first inverter stage in response to a second clock signal. The output of the shift register connects to the input of the first inverter stage. The registers include means for generating the first and second clock signals, and means for multiplexing the charge detector in each register to a common output.

摘要翻译： 公开了具有改进的再生电荷检测器的电荷耦合器件移位寄存器。 电荷检测器由第一和第二非时钟反相器级组成，用于响应于第一时钟信号将第一反相器级的输入耦合到第二反相器级的输出的门控装置，用于连接第二反相器级的输入的连接装置 逆变器级到第一反相器级的输出，以及反馈装置，用于响应于第二时钟信号连接第一反相器级的输入和输出。 移位寄存器的输出连接到第一个反相器级的输入端。 寄存器包括用于产生第一和第二时钟信号的装置，以及用于将每个寄存器中的电荷检测器复用到公共输出的装置。

公开(公告)号：US4056739A

公开(公告)日：1977-11-01

申请号：US710554

申请日：1976-08-02

申请人： John O. G. Darrow

发明人： John O. G. Darrow

IPC分类号： G01R19/165 ,  H03K5/08 ,  H03K5/18

CPC分类号： H03K5/08 ,  G01R19/1658

摘要： A fail-safe symmetrical solid-state polarized relay circuit having a positive and a negative level detector coupled to a source of periodic input signals. A pair of amplifiers for amplifying the a.c. oscillations produced by the level detectors. A plurality of rectifiers for rectifying the a.c. oscillations and for alternately producing a d.c. output voltage on a pair of output terminals in accordance with the positive and negative excursions of the periodic input signals.

摘要翻译： 一种故障安全对称固态极化继电器电路，其具有耦合到周期性输入信号源的正和负电平检测器。 一对放大器的放大器。 电平检测器产生的振荡。 多个整流器，用于整流交流 振荡和交替产生直流。 根据周期性输入信号的正偏移和负偏移，在一对输出端上输出电压。

公开(公告)号：US4054950A

公开(公告)日：1977-10-18

申请号：US681674

申请日：1976-04-29

申请人： James G. Boone

发明人： James G. Boone

IPC分类号： G11B20/14 ,  G11B20/12 ,  G11B27/30 ,  H04L7/033 ,  H04L7/04 ,  G06F1/04 ,  H03K5/18

CPC分类号： G11B20/12 ,  G11B27/3027 ,  H04L7/046 ,  H04L7/033

摘要： In order to detect the eminent reception of a valid bit serial message, a preamble constituting a string of predetermined number of clock pulses only is employed. Prior to detection of the preamble, each clock and data pulse from the raw data stream is applied to the increment input of a resettable counter. Each clock pulse is also used to trigger a monostable multivibrator which issues a pulse approximating three-fourths of a cell period. This pulse is ANDed with the next subsequent data period, and if a data "1" bit is detected, the satisfied condition is used to reset the counter. Thus, the counter can only reach a terminal count if a valid preamble is received. When the counter attains its terminal count, a latch flip-flop is set and a resultant "separation enable" signal issues to activate straightforward logic for separating the incoming clock and data pulses. Setting the latch also disables the preamble detection logic until an "end of data field" code is sensed whereupon the counter and latch are both reset to resume observation of the raw data stream for a preamble.

摘要翻译： 为了检测有效比特串行消息的显着接收，仅采用构成预定数量的时钟脉冲串的前导码。 在检测到前置码之前，将来自原始数据流的每个时钟和数据脉冲施加到可复位计数器的增量输入。 每个时钟脉冲也用于触发单稳态多谐振荡器，其发出接近单元周期的四分之三的脉冲。 该脉冲与下一个后续数据周期进行“与”运算，如果检测到数据“1”，则使用满足条件来复位计数器。 因此，如果接收到有效的前导码，则计数器只能达到终端计数。 当计数器达到其终端计数时，设置锁存触发器并产生结果“分离使能”信号以激活用于分离输入时钟和数据脉冲的直接逻辑。 设置锁存器还禁用前导码检测逻辑，直到感测到“数据字段结束”代码，然后计数器和锁存器都被复位以恢复对前导码的原始数据流的观察。

公开(公告)号：US4039813A

公开(公告)日：1977-08-02

申请号：US674712

申请日：1976-04-07

申请人： Glen Roy Kregness

发明人： Glen Roy Kregness

IPC分类号： G06F11/22 ,  G06F11/277 ,  G06F11/04 ,  H03K5/18

CPC分类号： G06F11/277

摘要： A self-test monitor and diagnostic apparatus which includes a test step counter, an error comparator apparatus, which may be a memory device loaded so as to predict the proper state of each of the lines to be monitored at each test step and which functions to detect any difference between what should be occurring at that test step and what is, in fact, occurring on the monitored line, and an error localization network which translates the detected errors into a displayable code for maintenance isolation.

公开(公告)号：US4038567A

公开(公告)日：1977-07-26

申请号：US669012

申请日：1976-03-22

申请人： Scott Clarence Lewis ,  Theodore Milton Redman ,  James Edward Rock ,  Donald Lawrence Wilder

发明人： Scott Clarence Lewis ,  Theodore Milton Redman ,  James Edward Rock ,  Donald Lawrence Wilder

IPC分类号： G11C11/417 ,  G11C7/00 ,  G11C11/34 ,  G11C11/4093 ,  G11C11/418 ,  H03K3/356 ,  H03K5/02 ,  H03K5/20 ,  H03K3/286 ,  H03K3/353 ,  H03K5/18

CPC分类号： H03K5/023 ,  G11C11/34 ,  G11C11/4093 ,  G11C11/418 ,  G11C7/00 ,  H03K3/35606 ,  H03K3/356095

摘要： A memory input signal dynamic logic buffer circuit for providing FET level complementary output signals in response to low level input signals. The circuit is compatible with a variety of bipolar transistor driving logic families as the input signal sensitivity may set external to the circuit. The circuit includes a cross-coupled dynamic latch responsive to gated input and reference signals. Voltage boosting capacitors coupled to the latch nodes provide for simultaneous setting of the latch and boosting of the output nodes, which are connected to dynamic output driver circuits.

公开(公告)号：US4025801A

公开(公告)日：1977-05-24

申请号：US687731

申请日：1976-05-19

申请人： William Milton Gosney

发明人： William Milton Gosney

IPC分类号： G11C19/28 ,  H03K3/356 ,  H03K5/18 ,  H03K3/286 ,  H03K3/353 ,  H03K5/20

CPC分类号： G11C19/285 ,  G11C19/28 ,  H03K3/35606 ,  H03K3/356078 ,  H03K3/356095

摘要： The disclosure relates to improved detectors for use in digital charge coupled device (CCD) applications as, for example, in a multiplexing system, for recreating full logic voltage levels by detecting extremely small amounts of charge available in CCD bits. This is accomplished by means of a flip-flop circuit wherein opposite nodes of the flip-flop are precharged to a predetermined intermediate level between a logical 0 and a logical 1, one of the nodes being a reference node and the other node being coupled to a CCD storage device. During sampling of the bits being read out from the CCD storage device, the detecting node of the flip-flop will have its voltage altered, either upwardly or downwardly, from the charge on the CCD being read out. This will cause an imbalance in the flip-flop and cause the flip-flop to conduct on only one side thereof, this being determined by the charge detected. In this way, a very low level signal can be detected and amplified to a full logic voltage level for readout.

摘要翻译： 本公开涉及用于例如在复用系统中的数字电荷耦合器件（CCD）应用中的改进的检测器，用于通过检测CCD位中可用的极小量的电荷来重建全逻辑电压电平。 这通过触发器电路来实现，其中触发器的相对节点被预充电到逻辑0和逻辑1之间的预定中间级，节点之一是参考节点，而另一个节点耦合到 CCD存储设备。 在从CCD存储装置读取的比特的采样期间，触发器的检测节点将从其被读出的CCD上的电荷向上或向下改变其电压。 这将导致触发器中的不平衡，并且引起触发器仅在其一侧进行，这由所检测的电荷决定。 以这种方式，可以检测到非常低电平的信号并将其放大到完全逻辑电压电平以进行读出。

公开(公告)号：US4005364A

公开(公告)日：1977-01-25

申请号：US698103

申请日：1976-06-21

申请人： Timothy M. Harrington

发明人： Timothy M. Harrington

IPC分类号： G01R23/15 ,  H03K5/26 ,  H03K5/18 ,  G01R23/10

CPC分类号： G01R23/15 ,  H03K5/26

摘要： A digital circuit determines the maximum frequency present in a first pulse train and indicates when a selected fraction of this maximum frequency is exceeded in subsequent pulse trains. The invention comprises a prescaler circuit for the purpose of reducing the frequency of the input pulse train to a level suitable for a digital period-measuring circuit; a digital period-measurement circuit that measures the period of the output of the prescaler and compares that measured value to a stored value; a frequency-multiplier circuit that produces the reference frequency used to measure the period in the period-measurement circuit; and a control circuit to operate the circuits in a first mode for storing a digital value representative of the maximum frequency present in the input pulse train, and in a second mode for comparing the frequency of subsequent pulse trains with the value stored in the first mode. The control circuit produces an output signal when the frequency of the subsequent pulse train exceeds a selected fraction of the maximum frequency present in the first pulse train.

摘要翻译： 数字电路确定存在于第一脉冲串中的最大频率，并且指示在随后的脉冲串中何时超出该最大频率的选定分数。 本发明包括预分频器电路，用于将输入脉冲串的频率降低到适合于数字周期测量电路的电平; 数字周期测量电路，其测量预分频器的输出周期，并将该测量值与存储值进行比较; 产生用于测量周期测量电路中的周期的参考频率的倍频电路; 以及控制电路，用于以第一模式操作电路，用于存储表示输入脉冲串中存在的最大频率的数字值，以及用于将后续脉冲序列的频率与存储在第一模式中的值进行比较的第二模式 。 当后续脉冲串的频率超过存在于第一脉冲串中的最大频率的选定分数时，控制电路产生输出信号。

公开(公告)号：US3976895A

公开(公告)日：1976-08-24

申请号：US559543

申请日：1975-03-18

申请人： James Teh-Zen Koo

发明人： James Teh-Zen Koo

IPC分类号： G01R19/165 ,  G11C11/4091 ,  H03K3/353 ,  H03K3/356 ,  H03K5/18 ,  H03K3/286 ,  H03K5/20

CPC分类号： H03K3/356095 ,  G01R19/16557 ,  G11C11/4091 ,  H03K3/353 ,  H03K3/356

摘要： A low power detector circuit consists of the basic four MOS transistors of an MOS flip-flop and includes another pair of MOS transistors as well as voltage equalization circuitry. The added pair of transistors and the cross coupling of the gates of two of the other transistors results in a detector circuit which automatically limits power dissipation at least by the time the proper output signal levels are attained.

摘要翻译： 低功率检测器电路由MOS触发器的基本四个MOS晶体管组成，并且包括另一对MOS晶体管以及电压均衡电路。 添加的一对晶体管和两个其他晶体管的栅极的交叉耦合导致检测器电路，其至少在达到适当的输出信号电平的时间时自动限制功率耗散。

公开(公告)号：US3922613A

公开(公告)日：1975-11-25

申请号：US53798875

申请日：1975-01-02

申请人： HONEYWELL INF SYSTEMS

发明人： ALLEN WILLIAM REED ,  DELORENZO JOHN D

IPC分类号： G11B20/14 ,  G11B5/45 ,  H03K5/18

CPC分类号： G11B20/1419

摘要： Double transition recorded information, such as phase encoded or frequency encoded information, is detected by use of a digital tracking oscillator which is responsive to either the data or the clock transitions of the recorded information and which produces a string of pulses in response thereto having a frequency which changes dependent upon the frequency of occurrence of the information. Clock pulses, and accordingly, a window, are thus generated, bracketing the data substantially in accordance with predetermined criteria, thereby enabling effective detection of the data included in the information. The digital tracking oscillator is adaptive to different propagation delays and drifts which may be introduced by the various circuit elements and thus needs no further adjustment therefor and may accordingly be manufactured on a single integrated circuit chip. The oscillator is also adaptive to changes in the frequency of the reading of the recorded information. This adaptive technique thus improves upon the effective detection of the data included in the information.

摘要翻译： 通过使用响应于记录信息的数据或时钟转换的数字跟踪振荡器来检测双转换记录信息，例如相位编码或频率编码信息，并响应于该脉冲产生一串脉冲，具有 变化的频率取决于信息的发生频率。 因此，产生时钟脉冲，因此产生窗口，基本上按照预定标准包围数据，从而能够有效地检测信息中包括的数据。 数字跟踪振荡器适应于可由各种电路元件引入的不同传播延迟和漂移，并且因此不需要进一步的调整，因此可以在单个集成电路芯片上制造。 振荡器也适应于读取记录信息的频率的变化。 因此，该自适应技术改进了对信息中包括的数据的有效检测。