公开(公告)号：US20110093752A1

公开(公告)日：2011-04-21

申请号：US12976042

申请日：2010-12-22

申请人： Emil Gizdarski

发明人： Emil Gizdarski

IPC分类号： G06F11/267

CPC分类号： G01R31/318547

摘要： Methods and apparatuses for synthesizing and/or implementing an augmented multimode compactor are described.

摘要翻译： 描述了用于合成和/或实现增强型多模式压实机的方法和装置。

公开(公告)号：US20110087939A1

公开(公告)日：2011-04-14

申请号：US12952837

申请日：2010-11-23

申请人： Lee D. Whetsel

发明人： Lee D. Whetsel

IPC分类号： G06F11/267

CPC分类号： G01R31/3177 ,  G01R31/3172 ,  G01R31/318536 ,  G01R31/318555 ,  G01R31/318572 ,  G06F1/10

摘要： Two common varieties of test interfaces exist for ICs and/or cores, the IEEE 1149.1 Test Access Port (TAP) interface and internal scan test ports. The TAP serves as a serial communication port for accessing a variety of circuitry including; IEEE 1149.1 boundary scan circuitry, built in self test circuitry, internal scan circuitry, IEEE 1149.4 mixed signal test circuitry, IEEE P5001 in-circuit emulation/debug circuitry, and IEEE P1532 in-system programming circuitry. Internal scan test ports serve as a serial communication port for primarily accessing internal scan circuitry within ICs and cores. Today, the TAP and internal scan test ports are typically viewed as being separate test interfaces, each utilizing different IC pins and/or core terminals. The need for different IC pins and/or core terminals is overcome by an interface in accordance with the disclosure that allows the TAP and internal scan test ports to be merged so they both can co-exist and operate from the same set of IC pins and/or core terminals. Further, this interface allows merged TAP and scan test port interfaces to be selected individually or in groups.

摘要翻译： IEEE 1149.1测试访问端口（TAP）接口和内部扫描测试端口存在IC和/或内核的两种常见的测试接口。 TAP用作用于访问各种电路的串行通信端口，包括： IEEE 1149.1边界扫描电路，内建自测电路，内部扫描电路，IEEE 1149.4混合信号测试电路，IEEE P5001在线仿真/调试电路和IEEE P1532系统编程电路。 内部扫描测试端口用作主要访问IC和内核内部扫描电路的串行通信端口。 今天，TAP和内部扫描测试端口通常被视为分离的测试接口，每个测试接口都使用不同的IC引脚和/或核心端子。 通过根据本公开的接口来克服对不同IC引脚和/或核心端子的需要，其允许TAP和内部扫描测试端口被合并，使得它们可以从同一组IC引脚共存和操作， /或核心终端。 此外，该接口允许单独或分组选择合并的TAP和扫描测试端口接口。

公开(公告)号：US20100095177A1

公开(公告)日：2010-04-15

申请号：US12250085

申请日：2008-10-13

申请人： Donato Orazio Forlenza ,  Orazio Pasquale Forlenza ,  Phong T. Tran

发明人： Donato Orazio Forlenza ,  Orazio Pasquale Forlenza ,  Phong T. Tran

IPC分类号： G01R31/3185 ,  G06F11/267

CPC分类号： G01R31/3183 ,  G01R31/318547

摘要： A method, apparatus and computer program product are provided for implementing diagnostics of transitional scan chain defects using structural Logic Built In Self Test (LBIST) test patterns. A LBIST test pattern is applied to the device under test and multiple system clock sequences with variable loop control are applied in a passing operating region and scan data is unloaded. The LBIST test pattern is applied to the device under test and multiple system clock sequences with variable loop control are applied in a failing operating region for the device under test and scan data is unloaded. Then the unload data from the passing operating region and the failing operating region are compared. The identified latches having different results are identified as potential AC defective latches. The identified potential AC defective latches are sent to a Physical Failure Analysis system.

摘要翻译： 提供了一种方法，设备和计算机程序产品，用于使用结构逻辑内置自检（LBIST）测试模式实现过渡扫描链缺陷的诊断。 将LBIST测试模式应用于被测设备，并且具有可变环路控制的多个系统时钟序列应用于通过的操作区域，并且扫描数据被卸载。 将LBIST测试模式应用于被测器件，并且将具有可变环路控制的多个系统时钟序列应用于被测器件的故障操作区域，并且扫描数据被卸载。 然后比较从通过的操作区域和故障操作区域卸载数据。 具有不同结果的识别的锁存器被识别为潜在的AC缺陷锁存器。 所识别的潜在AC缺陷锁存器被发送到物理故障分析系统。

公开(公告)号：US20090164845A1

公开(公告)日：2009-06-25

申请号：US12396174

申请日：2009-03-02

申请人： Lee D. Whetsel

发明人： Lee D. Whetsel

IPC分类号： G06F11/267

CPC分类号： G01R31/3177 ,  G01R31/318555 ,  G01R31/318563

摘要： A device test architecture and interface is provided to enable efficient testing embedded cores within devices. The test architecture interfaces to standard IEEE 1500 core test wrappers and provides high test data bandwidth to the wrappers from an external tester. The test architecture includes compare circuits that allow for comparison of test response data to be performed within the device. The test architecture further includes a memory for storing the results of the test response comparisons. The test architecture includes a programmable test controller to allow for various test control operations by simply inputting an instruction to the programmable test controller from the external tester. The test architecture includes a selector circuit for selecting a core for testing. Additional features and embodiments of the device test architectures are also disclosed.

摘要翻译： 提供了一种器件测试体系结构和接口，可以高效地测试器件内的嵌入式内核。 测试架构与标准IEEE 1500核心测试包装器相连接，并从外部测试仪器向封装器提供高测试数据带宽。 测试架构包括比较电路，允许比较要在设备内执行的测试响应数据。 测试架构还包括用于存储测试响应比较结果的存储器。 测试架构包括一个可编程测试控制器，通过从外部测试仪简单地向可编程测试控制器输入指令来允许各种测试控制操作。 测试架构包括用于选择用于测试的核心的选择器电路。 还公开了设备测试架构的附加特征和实施例。

公开(公告)号：US20090083596A1

公开(公告)日：2009-03-26

申请号：US12235341

申请日：2008-09-22

申请人： Emil Gizdarski

发明人： Emil Gizdarski

IPC分类号： G01R31/3177 ,  G06F11/267

CPC分类号： G01R31/318547 ,  G06F17/505 ,  G06F2217/14

摘要： Methods and apparatuses for synthesizing and/or implementing an augmented multimode compactor are described.

公开(公告)号：US20050251358A1

公开(公告)日：2005-11-10

申请号：US10740723

申请日：2003-12-18

申请人： James Van Dyke ,  John Montrym ,  Michael Nagy ,  Sean Treichler

发明人： James Van Dyke ,  John Montrym ,  Michael Nagy ,  Sean Treichler

IPC分类号： G01M19/00 ,  G01R31/26 ,  G06F11/00 ,  G06F11/267 ,  G06F17/50 ,  G09G5/02

CPC分类号： G01R31/318544 ,  G01R31/31704 ,  G01R31/3185 ,  G05B99/00 ,  G06F11/2289 ,  G06F11/267 ,  G06F19/00 ,  H01L22/22 ,  H01L2924/0002 ,  H01L2924/00

摘要： The present invention systems and methods facilitate increased die yields by flexibly changing the operational characteristics of functional components in an integrated circuit die. The present invention system and method enable integrated circuit chips with defective functional components to be salvaged. Defective functional components in the die are disabled in a manner that maintains the basic functionality of the chip. A chip is tested and a functional component configuration process is performed on the chip based upon results of the testing. If an indication of a defective functional component is received, the functional component is disabled. Workflow is diverted from disabled functional components to enabled functional components.

摘要翻译： 本发明的系统和方法通过灵活地改变集成电路管芯中的功能部件的操作特性而有利于提高管芯的产量。 本发明的系统和方法使具有缺陷功能部件的集成电路芯片能够被打捞。 芯片中缺陷的功能组件以保持芯片的基本功能的方式被禁用。 测试芯片，并根据测试结果在芯片上执行功能组件配置过程。 如果接收到缺陷功能组件的指示，则功能组件被禁用。 工作流程从禁用的功能组件转移到启用的功能组件。

公开(公告)号：US06963814B2

公开(公告)日：2005-11-08

申请号：US10734010

申请日：2003-12-11

申请人： John David Jones ,  Steven Michael Hausman

发明人： John David Jones ,  Steven Michael Hausman

IPC分类号： G06F9/45 ,  G06F11/26 ,  G06F11/267 ,  G06F19/00

CPC分类号： G06F11/261 ,  G06F11/221

摘要： Certain exemplary embodiments comprise a method for acceptance testing a fieldbus component configuration program. The method can comprise providing simulated input information to the fieldbus component configuration program. The method can further comprise comparing outputs from the fieldbus component configuration program to predetermined outputs. In certain exemplary embodiments, the method can comprise determining if the fieldbus component configuration program output is faulty.

摘要翻译： 某些示例性实施例包括用于验证现场总线组件配置程序的方法。 该方法可以包括向现场总线组件配置程序提供模拟输入信息。 该方法还可以包括将来自现场总线组件配置程序的输出与预定输出进行比较。 在某些示例性实施例中，该方法可以包括确定现场总线组件配置程序输出是否有故障。

公开(公告)号：US20050246594A1

公开(公告)日：2005-11-03

申请号：US10709156

申请日：2004-04-16

申请人： Ramon Co ,  Tat Lai ,  David Sun

发明人： Ramon Co ,  Tat Lai ,  David Sun

IPC分类号： G06F11/00 ,  G06F11/267 ,  G11C29/24

CPC分类号： G11C29/24 ,  G06F11/2215 ,  G11C5/04 ,  G11C2029/5602

摘要： Memory modules with an extra dynamic-random-access memory (DRAM) chip for storing error-correction code (ECC) are tested on a personal computer (PC) motherboard tester using a cross-over extender card inserted into a memory module socket on the motherboard. ECC code generated on the motherboard is normally stored in the extra ECC DRAM chip, preventing test patterns such as checkerboards and walking-ones to be written directly to the ECC DRAM chip. During testing, the cross-over extender card routes signals from the motherboard for one of the data DRAM chips to the ECC DRAM chip, while the ECC code is routed to one of the data DRAM chips. The checkerboard or other test pattern is thus written and read from the ECC DRAM chip that normally stores the ECC code. The cross-over extender card can be hardwired, or can have a switch to allow normal operation or testing of the ECC DRAM chip.

摘要翻译： 具有用于存储纠错码（ECC）的额外动态随机存取存储器（DRAM）芯片的存储器模块在个人计算机（PC）主板测试器上使用插入到内存模块插槽中的跨越延长卡进行测试 母板。 在主板上产生的ECC代码通常存储在额外的ECC DRAM芯片中，防止诸如棋盘和步行的测试图案直接写入ECC DRAM芯片。 在测试期间，交叉扩展卡将来自主板的信号从数据DRAM芯片中的一个传送到ECC DRAM芯片，而ECC代码被路由到数据DRAM芯片之一。 因此，棋盘或其他测试图案由通常存储ECC代码的ECC DRAM芯片写入和读出。 交叉扩展卡可以是硬连线的，或者可以有开关来允许ECC DRAM芯片的正常操作或测试。

公开(公告)号：US20050240850A1

公开(公告)日：2005-10-27

申请号：US10967280

申请日：2004-10-19

申请人： Akihiko Ohwada ,  Tatsumi Nakada ,  Hitoshi Yamanaka

发明人： Akihiko Ohwada ,  Tatsumi Nakada ,  Hitoshi Yamanaka

IPC分类号： G01R31/28 ,  G01R31/3185 ,  G06F9/26 ,  G06F9/34 ,  G06F11/00 ,  G06F11/22 ,  G06F11/263 ,  G06F11/267 ,  G06F12/00 ,  G06F12/02 ,  G06F12/04 ,  G06F12/08 ,  G06F12/10 ,  G06F12/14 ,  G06F12/16 ,  G06F13/00 ,  G06F13/28 ,  H01L21/822 ,  H01L27/04

CPC分类号： G06F11/263 ,  G01R31/318547 ,  G06F11/267

摘要： In processors having a multicore, such as CMPs, an independent MISR test pattern compression circuit is provided for each logic block in a multicore processor such as a CMP comprising a plurality of processor cores makes it possible to perform LSI tests more efficiently. A processor comprises a plurality of logic block circuits, plurality of logic block circuits comprising at least a first processor core circuit and a second processor core circuit, each processor core circuit having a scan chain circuit and being operable independently, and a common block circuit having a scan chain circuit and a cache circuit that is shared by the first processor core circuits and the second processor core circuits, the processor further comprising, for each logic block, a test pattern generating circuit operable to generate a test pattern and input the test pattern to the scan chain of each logic block circuit, and a test pattern compression circuit operable to accept as input and compress the test pattern output by the scan chain of each logic block circuit.

摘要翻译： 在具有多核（诸如CMP）的处理器中，为包括多个处理器核心的多核处理器（例如CMP）中的每个逻辑块提供独立的MISR测试图案压缩电路，使得可以更有效地执行LSI测试。 处理器包括多个逻辑块电路，多个逻辑块电路至少包括第一处理器核心电路和第二处理器核心电路，每个处理器核心电路具有扫描链电路并且可独立操作;以及公共块电路，其具有 扫描链电路和由第一处理器核心电路和第二处理器核心电路共享的高速缓存电路，处理器还包括针对每个逻辑块的测试图形生成电路，其可操作以产生测试图案并输入测试图案 到每个逻辑块电路的扫描链，以及测试图案压缩电路，其可操作以接受作为输入并压缩由每个逻辑块电路的扫描链输出的测试图案。

公开(公告)号：US20050240837A1

公开(公告)日：2005-10-27

申请号：US11115562

申请日：2005-04-27

申请人： Laurent Dubois ,  Philippe Raoul ,  Gerhard Mersch

发明人： Laurent Dubois ,  Philippe Raoul ,  Gerhard Mersch

IPC分类号： G06F11/267 ,  A61K51/00 ,  A61M36/14 ,  G01R31/28

CPC分类号： G06F11/2236 ,  H04L1/24

摘要： A method of operating a control unit (CU) begins by performing a power on reset. If the CU receives a start-up message within a predefined time period after the reset, then the CU enters a diagnostic mode in which a diagnostic communication can be established with a diagnostic unit. If no start-up message is received within the predefined time period, the CU enters a normal mode of operation. The CU includes a memory designated to store data unique for a respective vehicle type, a first communication module allowing communication via a bus system under a first protocol for normal operation of the CU, and a second communication module allowing communication via the bus system under a second protocol for accessing the memory.

摘要翻译： 通过执行上电复位来开始操作控制单元（CU）的方法。 如果CU在复位之后的预定义时间段内接收到启动消息，则CU进入诊断模式，在诊断模式中可以与诊断单元建立诊断通信。 如果在预定时间段内没有收到启动消息，则CU进入正常操作模式。 CU包括指定用于存储针对相应车辆类型唯一的数据的存储器，第一通信模块，其允许经由总线系统以第一协议进行通信，以便CU的正常操作;以及第二通信模块，其允许经由总线系统在 用于访问存储器的第二协议。