公开(公告)号：US20220297234A1

公开(公告)日：2022-09-22

申请号：US17832832

申请日：2022-06-06

申请人： Taiwan Semiconductor Manufacturing Co., Ltd.

发明人： Chansyun David Yang ,  Li-Te Lin ,  Pinyen Lin

IPC分类号： B23K26/348 ,  H01L21/3115 ,  B23K26/067 ,  B23K26/06 ,  H01L21/311

摘要： A semiconductor fabrication apparatus includes a source chamber being operable to generate charged particles; and a processing chamber integrated with the source chamber and configured to receive the charged particles from the source chamber. The processing chamber includes a wafer stage being operable to secure and move a wafer, and a laser-charged particles interaction module that further includes a laser source to generate a first laser beam; a beam splitter configured to split the first laser beam into a second laser beam and a third laser beam; and a mirror configured to reflect the third laser beam such that the third laser beam is redirected to intersect with the second laser beam to form a laser interference pattern at a path of the charged particles, and wherein the laser interference pattern modulates the charged particles by in a micron-zone mode for processing the wafer using the modulated charged particles.

公开(公告)号：US11444183B2

公开(公告)日：2022-09-13

申请号：US17092566

申请日：2020-11-09

申请人： Semiconductor Manufacturing International (Shanghai) Corporation ,  Semiconductor Manufacturing International (Beijing) Corporation

发明人： Nan Wang

IPC分类号： H01L29/66 ,  H01L29/78 ,  H01L29/423 ,  H01L29/06 ,  H01L21/762 ,  H01L21/311 ,  H01L21/3115 ,  H01L21/02 ,  H01L21/28

摘要： A semiconductor structure and a formation method thereof are provided. In one form, the method includes: providing a base; patterning the base to form a substrate and discrete fins and pseudo fins which protrude from the substrate, wherein the fins are located in a device region, and the pseudo fins are located in isolation regions; removing the pseudo fins in the isolation regions; forming isolation layers on the substrate exposed by the fins, wherein the isolation layers cover part of the side walls of the fins; and thinning the isolation layers in the isolation regions, wherein the remaining isolation layers in the isolation regions are regarded as target isolation layers, and the surfaces of the target isolation layers are lower than the surfaces of the isolation layers between the discrete fins. Since the surfaces of the target isolation layers are lower than the surfaces of the isolation layers between the discrete fins, the volume of the target isolation layers is correspondingly reduced, and then stress generated by the target isolation layers on the fins is lowered, which causes the stress on both sides of the fins to be balanced, avoids the problem of bending or tilting of the fins in the device region in case of stress imbalance and improves the electrical performance of the semiconductor structure.

公开(公告)号：US20220216327A1

公开(公告)日：2022-07-07

申请号：US17140453

申请日：2021-01-04

申请人： Taiwan Semiconductor Manufacturing Co., Ltd.

发明人： Shahaji B. MORE ,  Chandrashekhar Prakash Savant

IPC分类号： H01L29/66 ,  H01L29/51 ,  H01L29/78 ,  H01L21/3115

摘要： The present disclosure describes method to form a semiconductor device having a gate dielectric layer with controlled doping. The method includes forming a gate dielectric layer on a fin structure, forming a diffusion barrier layer on the gate dielectric layer, and forming a dopant source layer on the diffusion barrier layer. The gate dielectric layer includes an interfacial layer on the fin structure and a high-k dielectric layer on the interfacial layer. A dopant of the dopant source layer diffuses into the gate dielectric layer. The method further includes doping a portion of the interfacial layer with the dopant and removing the dopant source layer. The portion of the interfacial layer is adjacent to the high-k dielectric layer.

公开(公告)号：US11380589B2

公开(公告)日：2022-07-05

申请号：US16662845

申请日：2019-10-24

申请人： TESSERA, INC.

发明人： Veeraraghavan S. Basker ,  Kangguo Cheng ,  Ali Khakifirooz

IPC分类号： H01L21/8234 ,  H01L27/088 ,  H01L29/06 ,  H01L29/423 ,  H01L21/265 ,  H01L21/762 ,  H01L21/306 ,  H01L29/66 ,  H01L21/308 ,  H01L21/311 ,  H01L21/32 ,  H01L21/3213 ,  H01L21/027 ,  H01L29/78 ,  H01L21/3115 ,  H01L21/3215

摘要： An array of semiconductor fins is formed on a top surface of a substrate. A dielectric material liner is formed on the surfaces of the array of semiconductor fins. A photoresist layer is applied and patterned such that sidewalls of an opening in the photoresist layer are parallel to the lengthwise direction of the semiconductor fins, and are asymmetrically laterally offset from a lengthwise direction passing through the center of mass of a semiconductor fin to be subsequently removed. An angled ion implantation is performed to convert a top portion of dielectric material liner into a compound material portion. The compound material portion is removed selective to the remaining dielectric material liner, and the physically exposed semiconductor fin can be removed by an etch or converted into a dielectric material portion by a conversion process. The dielectric material liner can be removed after removal of the semiconductor fin.

公开(公告)号：US20220190127A1

公开(公告)日：2022-06-16

申请号：US17686978

申请日：2022-03-04

申请人： Taiwan Semiconductor Manufacturing Company, Ltd.

发明人： Shih-Wen HUANG ,  Chung-Ting KO ,  Hong-Hsien KE ,  Chia-Hui LIN ,  Tai-Chun HUANG

IPC分类号： H01L29/417 ,  H01L29/78 ,  H01L29/08 ,  H01L29/45 ,  H01L21/768 ,  H01L21/02 ,  H01L29/66 ,  H01L21/8234 ,  H01L21/311 ,  H01L21/3115

摘要： A semiconductor structure is provided. The semiconductor structure includes a gate structure, a source/drain structure, a barrier layer, and a glue layer. The gate structure is over a fin structure. The source/drain structure is in the fin structure and adjacent to the gate structure. The barrier layer is over the source/drain structure. The glue layer is adjacent to the barrier layer. The glue layer has an extending portion in direct contact with the gate structure.

公开(公告)号：US20220181451A1

公开(公告)日：2022-06-09

申请号：US17651843

申请日：2022-02-21

申请人： Taiwan Semiconductor Manufacturing Co., Ltd.

发明人： Tsan-Chun Wang ,  Su-Hao Liu ,  Liang-Yin Chen ,  Huicheng Chang ,  Yee-Chia Yeo

IPC分类号： H01L29/40 ,  H01L29/45 ,  H01L21/3115 ,  H01L21/033 ,  H01L21/285

摘要： A method of forming a semiconductor device includes forming a source/drain region and a gate electrode adjacent the source/drain region, forming a hard mask over the gate electrode, forming a bottom mask over the source/drain region, wherein the gate electrode is exposed, and performing a nitridation process on the hard mask over the gate electrode. The bottom mask remains over the source/drain region during the nitridation process and is removed after the nitridation. The method further includes forming a silicide over the source/drain region after removing the bottom mask.

公开(公告)号：US11355342B2

公开(公告)日：2022-06-07

申请号：US16440354

申请日：2019-06-13

申请人： NANYA TECHNOLOGY CORPORATION

发明人： Kuo-Hui Su

IPC分类号： H01L21/3115 ,  H01L21/033 ,  H01L21/02

摘要： A semiconductor structure includes a base layer with a top surface and a plurality of processed areas. A primary pattern is disposed on the top surface of the base layer, wherein the primary pattern has a pattern top surface, a processed area on the pattern top surface, and a sidewall, and the primary pattern has a first critical dimension, and the processed areas are on the part of the top surface of the base layer exposed by the primary pattern. A secondary pattern is disposed on the sidewall of the primary pattern, wherein the secondary pattern has a second critical dimension, and the second critical dimension is smaller than the first critical dimension.

公开(公告)号：US11351635B2

公开(公告)日：2022-06-07

申请号：US16653401

申请日：2019-10-15

申请人： Taiwan Semiconductor Manufacturing Co., Ltd.

发明人： Chansyun David Yang ,  Li-Te Lin ,  Pinyen Lin

IPC分类号： B23K26/348 ,  H01L21/3115 ,  B23K26/067 ,  B23K26/06 ,  H01L21/311

摘要： A semiconductor fabrication apparatus includes a source chamber being operable to generate charged particles; and a processing chamber integrated with the source chamber and configured to receive the charged particles from the source chamber. The processing chamber includes a wafer stage being operable to secure and move a wafer, and a laser-charged particles interaction module that further includes a laser source to generate a first laser beam; a beam splitter configured to split the first laser beam into a second laser beam and a third laser beam; and a mirror configured to reflect the third laser beam such that the third laser beam is redirected to intersect with the second laser beam to form a laser interference pattern at a path of the charged particles, and wherein the laser interference pattern modulates the charged particles by in a micron-zone mode for processing the wafer using the modulated charged particles.

公开(公告)号：US11342454B2

公开(公告)日：2022-05-24

申请号：US16908305

申请日：2020-06-22

申请人： Taiwan Semiconductor Manufacturing Company, Ltd.

发明人： Chia-Ling Chan ,  Meng-Yueh Liu ,  Wei-Ken Lin

IPC分类号： H01L21/22 ,  H01L21/31 ,  H01L21/82 ,  H01L29/78 ,  H01L29/66 ,  H01L29/06 ,  H01L21/311 ,  H01L21/3115 ,  H01L21/225 ,  H01L21/8238

摘要： In accordance with some embodiments, a method is provided. The method includes: forming a semiconductor fin protruding from a substrate; depositing a spacer layer over the semiconductor fin; after the depositing the spacer layer over the semiconductor fin, implanting a first dopant in the spacer layer and depositing a dopant layer of the first dopant on the spacer layer in alternating repeating steps; removing the dopant layer; and performing a thermal anneal process to drive the first dopant into the semiconductor fin from the spacer layer.

公开(公告)号：US20220157847A1

公开(公告)日：2022-05-19

申请号：US17117690

申请日：2020-12-10

申请人： YANGTZE MEMORY TECHNOLOGIES CO., LTD.

发明人： Kun Zhang ,  Linchun Wu ,  Wenxi Zhou ,  Zhiliang Xia ,  Zongliang Huo

IPC分类号： H01L27/11582 ,  H01L25/065 ,  H01L25/18 ,  H01L23/00 ,  H01L27/11556 ,  H01L29/04 ,  H01L29/16 ,  H01L29/10 ,  H01L21/225 ,  H01L21/02 ,  H01L21/3205 ,  H01L21/3115 ,  H01L21/3215 ,  H01L21/311 ,  H01L21/3213

摘要： A 3D memory device includes a memory stack including interleaved stack conductive layers and stack dielectric layers, a semiconductor layer, and a channel structure extending vertically through the memory stack into the semiconductor layer. A first lateral dimension of a first portion of the channel structure facing the semiconductor layer is greater than a second lateral dimension of a second portion of the channel structure facing the memory stack. The channel structure includes a memory film and a semiconductor channel A first doping concentration of part of the semiconductor channel in the first portion of the channel structure is greater than a second doping concentration of part of the semiconductor channel in the second portion of the channel structure.