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公开(公告)号：US11751394B2
公开(公告)日：2023-09-05
申请号：US17544814
申请日：2021-12-07
发明人： Linchun Wu , Shan Li , Zhiliang Xia , Kun Zhang , Wenxi Zhou , Zongliang Huo
IPC分类号： H10B43/27 , H01L21/8234 , H01L29/417
CPC分类号： H10B43/27 , H01L21/823487 , H01L29/41741
摘要： Embodiments of 3D memory devices and methods for forming the same are disclosed. In an example, a 3D memory device includes a doped region of a substrate. The doped region includes dopants of a first type. The 3D memory device also includes a semiconductor layer on the doped region. The semiconductor layer includes dopants of a second type. The first type and the second type are different from each other. The 3D memory device also includes a memory stack having interleaved conductive layers and dielectric layers on the semiconductor layer. The 3D memory device further includes a channel structure extending vertically through the memory stack and the semiconductor layer into the doped region, a semiconductor plug extending vertically into the doped region, the semiconductor plug comprising dopants of the second type, and a source contact structure extending vertically through the memory stack to be in contact with the semiconductor plug.
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公开(公告)号：US11562945B2
公开(公告)日：2023-01-24
申请号：US17020473
申请日：2020-09-14
发明人： Linchun Wu , Kun Zhang , Zhong Zhang , Wenxi Zhou , Zhiliang Xia
IPC分类号： H01L23/48 , H01L21/48 , H01L27/11565 , H01L27/1157 , H01L27/11573 , H01L27/11582
摘要： Embodiments of methods for forming contact structures and semiconductor devices thereof are disclosed. In an example, a semiconductor device includes an insulating layer, a conductive layer over the insulating layer, and a spacer structure in the conductive layer and in contact with the insulating layer. The semiconductor device also includes a first contact structure in the spacer structure and extending vertically through the insulating layer. The first contact structure includes a first contact portion and a second contact portion in contact with each other. An upper surface of the second contact portion is coplanar with an upper surface of the conductive layer.
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公开(公告)号：US20210320094A1
公开(公告)日：2021-10-14
申请号：US16881294
申请日：2020-05-22
发明人： Kun Zhang , Linchun Wu , Wenxi Zhou , Zhiliang Xia , Zongliang Huo
IPC分类号： H01L25/18 , H01L25/065 , H01L23/00 , H01L25/00
摘要： Embodiments of 3D memory devices and methods for forming the same are disclosed. In an example, a 3D memory device includes a substrate, a peripheral circuit on the substrate, a memory stack including interleaved conductive layers and dielectric layers above the peripheral circuit, a first semiconductor layer above the memory stack, a second semiconductor layer above and in contact with the first semiconductor layer, a plurality of channel structures each extending vertically through the memory stack and the first semiconductor layer, and a source contact above the memory stack and in contact with the second semiconductor layer.
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公开(公告)号：US11647632B2
公开(公告)日：2023-05-09
申请号：US17085305
申请日：2020-10-30
发明人： Kun Zhang , Linchun Wu , Zhong Zhang , Wenxi Zhou , Zongliang Huo
IPC分类号： H01L27/1158 , H01L25/18 , H01L21/768 , H01L23/00 , H01L25/00 , H01L27/11582
CPC分类号： H01L27/11582 , H01L21/76898 , H01L24/08 , H01L24/32 , H01L25/18 , H01L25/50 , H01L2224/08145 , H01L2224/32145
摘要： Embodiments of 3D memory devices and methods for forming the same are disclosed. In an example, a 3D memory device includes a memory stack, a first semiconductor layer, a supporting structure, a second semiconductor layer, and a plurality of channel structures. The memory stack includes vertically interleaved conductive layers and dielectric layers and has a core array region and a staircase region in a plan view. The first semiconductor layer is above and overlaps the core array region of the memory stack. The supporting structure is above and overlaps the staircase region of the memory stack. The supporting structure and the first semiconductor layer are coplanar. The second semiconductor layer is above and in contact with the first semiconductor layer and the supporting structure. Each channel structure extends vertically through the core array region of the memory stack and the first semiconductor layer into the second semiconductor layer.
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公开(公告)号：US11626416B2
公开(公告)日：2023-04-11
申请号：US16881324
申请日：2020-05-22
发明人： Kun Zhang , Linchun Wu , Wenxi Zhou , Zhiliang Xia , Zongliang Huo
IPC分类号： H01L27/11582 , H01L25/00 , H01L27/11565 , H01L27/1157 , H01L27/11573
摘要： Embodiments of 3D memory devices and methods for forming the same are disclosed. In an example, a method for forming a 3D memory device is disclosed. A sacrificial layer above a second semiconductor layer at a first side of a substrate and a dielectric stack on the sacrificial layer are subsequently formed. A channel structure extending vertically through the dielectric stack and the sacrificial layer into the second semiconductor layer is formed. The sacrificial layer is replaced with a first semiconductor layer in contact with the second semiconductor layer. The dielectric stack is replaced with a memory stack, such that the channel structure extends vertically through the memory stack and the first semiconductor layer into the second semiconductor layer. A source contact is formed at a second side opposite to the first side of the substrate to be in contact with the second semiconductor layer.
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公开(公告)号：US20230059524A1
公开(公告)日：2023-02-23
申请号：US17570123
申请日：2022-01-06
发明人： Linchun Wu , Kun Zhang , Wenxi Zhou , Zhiliang Xia , Wei Xie , Di Wang , Bingguo Wang , Zongliang Huo
IPC分类号： H01L27/11582 , H01L27/11556
摘要： A three-dimensional (3D) memory device includes a stack structure having interleaved conductive layers and dielectric layers, and a channel structure extending through the stack structure along a first direction. The channel structure is in contact with a source of the 3D memory device at a bottom portion of the channel structure. The channel structure includes a semiconductor channel, and a memory film over the semiconductor channel. The memory film includes a first angled structure, and a first diameter of the memory film at the bottom portion below the first angled structure is smaller than a second diameter of the memory film at an upper portion above the first angled structure.
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公开(公告)号：US11574921B2
公开(公告)日：2023-02-07
申请号：US16896571
申请日：2020-06-09
发明人： Linchun Wu
IPC分类号： H01L27/11 , H01L27/11582 , G11C16/04 , G11C16/16 , G11C16/26 , H01L27/11524 , H01L27/11556 , H01L27/1157
摘要： Three-dimensional (3D) NAND memory devices and methods are provided. In one aspect, a fabrication method includes depositing a cover layer over a substrate, depositing a layer stack over the cover layer, performing a first epitaxial growth to deposit a first epitaxial layer on a side portion of a channel layer that extends through the layer stack, removing the cover layer to expose a portion of the substrate, performing a second epitaxial growth to deposit a second epitaxial layer on the portion of the substrate, and performing a third epitaxial growth to deposit a third epitaxial layer on the second epitaxial layer. The second and third epitaxial layers are configured to provide separate electrical current paths for an erase operation and a read operation.
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公开(公告)号：US11488977B2
公开(公告)日：2022-11-01
申请号：US17147396
申请日：2021-01-12
发明人： Linchun Wu , Kun Zhang , Wenxi Zhou , Zhiliang Xia
IPC分类号： H01L27/11582 , H01L21/768 , H01L21/285
摘要： Embodiments of 3D memory devices and methods for forming the same are disclosed. In an example, a method for forming a 3D memory device is disclosed. A first polysilicon layer, a dielectric sacrificial layer, a second polysilicon layer, and a dielectric stack are sequentially formed above a substrate. A channel structure extending vertically through the dielectric stack, the second polysilicon layer, and the dielectric sacrificial, and into the first polysilicon layer is formed. An opening extending vertically through the dielectric stack and the second polysilicon layer, and extending vertically into or through the dielectric sacrificial layer to expose part of the dielectric sacrificial layer, and a polysilicon spacer along part of a sidewall of the opening are formed. The dielectric sacrificial layer is replaced, through the opening, with a third polysilicon layer between the first and second polysilicon layers.
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公开(公告)号：US11456290B2
公开(公告)日：2022-09-27
申请号：US16881294
申请日：2020-05-22
发明人： Kun Zhang , Linchun Wu , Wenxi Zhou , Zhiliang Xia , Zongliang Huo
IPC分类号： H01L25/18 , H01L25/065 , H01L23/00 , H01L25/00
摘要： Embodiments of 3D memory devices and methods for forming the same are disclosed. In an example, a 3D memory device includes a substrate, a peripheral circuit on the substrate, a memory stack including interleaved conductive layers and dielectric layers above the peripheral circuit, a first semiconductor layer above the memory stack, a second semiconductor layer above and in contact with the first semiconductor layer, a plurality of channel structures each extending vertically through the memory stack and the first semiconductor layer, and a source contact above the memory stack and in contact with the second semiconductor layer.
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公开(公告)号：US12048148B2
公开(公告)日：2024-07-23
申请号：US17084401
申请日：2020-10-29
发明人： Linchun Wu , Kun Zhang , Wenxi Zhou , Zhiliang Xia , Zongliang Huo
摘要： Embodiments of 3D memory devices and methods for forming the same are disclosed. In an example, a 3D memory device includes an insulating layer, a semiconductor layer, a memory stack including interleaved conductive layers and dielectric layers, a source contact structure extending vertically through the insulating layer from an opposite side of the insulating layer with respect to the semiconductor layer to be in contact with the semiconductor layer, and a channel structure extending vertically through the memory stack and the semiconductor layer into the insulating layer or the source contact structure.
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