公开(公告)号：US20070084925A1

公开(公告)日：2007-04-19

申请号：US11564864

申请日：2006-11-30

Applicant: Romain Palmade

Inventor： Romain Palmade

IPC: G06K7/08 ,  G06K19/06

CPC classification number: G06K7/10346 ,  G06K7/10297 ,  G06K19/0723

Abstract: A contactless electronic IC card (10), includes a communication device (14) for communicating with a contactless electronic IC card reader (12) in accordance with the ISO 14443-4 standard, a contact type electronic IC card operating system (16) communicating by APDU command and APDU response in accordance with the ISO 7816-4 standard, and a protocol conversion interface (18) between the communication device (14) and the operating system (16).

Abstract translation: 一种非接触式电子IC卡（10），包括：用于与根据ISO 14443-4标准的非接触电子IC卡读取器（12）通信的通信设备（14）;接触型电子IC卡操作系统（16），其通信 通过根据ISO 7816-4标准的APDU命令和APDU响应，以及在通信设备（14）和操作系统（16）之间的协议转换接口（18）。

公开(公告)号：US20070082631A1

公开(公告)日：2007-04-12

申请号：US11530215

申请日：2006-09-08

Applicant: Fabien Pousset ,  Frederic Rivoirard

Inventor： Fabien Pousset ,  Frederic Rivoirard

IPC: G06F3/033

CPC classification number: H03F1/32 ,  H03F1/3211 ,  H03F3/45085 ,  H03F3/45538 ,  H03F2203/30024 ,  H03F2203/45154

Abstract: A transconducting device includes at least one transistor having a control electrode for receiving an input signal whose frequency spectrum contains two different frequencies, an output electrode for delivering an output signal, and a third electrode. The transconducting device further includes a voltage source for delivering a DC reference voltage, and a feedback controller for feedback-controlling the voltage on the third electrode to the DC reference voltage using a negative feedback loop. The negative feedback loop includes resistive damping, connects the third electrode and the control electrode, and has an open-loop gain greater than unity at a frequency equal to the frequency separation between the two different frequencies.

Abstract translation: 跨导器件包括至少一个具有用于接收频谱包含两个不同频率的输入信号的控制电极，用于传送输出信号的输出电极和第三电极的晶体管。 所述跨导器件还包括用于传送直流参考电压的电压源和用于使用负反馈回路将所述第三电极上的电压反馈至所述直流参考电压的反馈控制器。 负反馈回路包括电阻阻尼，连接第三电极和控制电极，并且在等于两个不同频率之间的频率间隔的频率处具有大于单位的开环增益。

公开(公告)号：US07202137B2

公开(公告)日：2007-04-10

申请号：US10850040

申请日：2004-05-20

Applicant: Philippe Delpech ,  Christophe Regnier ,  Sebastien Cremer ,  Stephane Monfray

Inventor： Philippe Delpech ,  Christophe Regnier ,  Sebastien Cremer ,  Stephane Monfray

IPC: H01L21/20

CPC classification number: H01L28/40 ,  H01L21/76264 ,  H01L29/66772 ,  H01L29/78648

Abstract: A process for producing an integrated electronic circuit. The process begins with the production of a first electronic component and a second electronic component that are superposed on top of a substrate. A volume of temporary material is formed on the substrate at the position of the second electronic component. The first electronic component is then produced above the volume of temporary material relative to the substrate, and then the second electronic component is produced using at least one shaft for access to the temporary material. The first electronic component may be an active component and the second electronic component may be a passive component.

Abstract translation: 一种集成电子电路的制造方法。 该过程开始于重叠在基板顶部上的第一电子部件和第二电子部件的制造。 在第二电子部件的位置处，在基板上形成一定量的临时材料。 然后在临时材料的体积上方相对于基板制造第一电子部件，然后使用至少一个轴来制造第二电子部件，用于接近临时材料。 第一电子部件可以是有源部件，第二电子部件可以是无源部件。

公开(公告)号：US07188259B1

公开(公告)日：2007-03-06

申请号：US09914172

申请日：2000-02-25

Applicant: Fabrice Romain

Inventor： Fabrice Romain

IPC: G06F9/06 ,  G06F21/00

CPC classification number: H04L9/003 ,  G06F21/755 ,  G06F21/85 ,  G06F2207/7219 ,  G06F2211/007 ,  G06F2221/2123 ,  H04L2209/08

Abstract: A method for providing security to a chaining of useful operations of the same type, performed by an electronic circuit executing an algorithm, randomly introduces one or more dummy operations in the chaining of operations. This prevents any fraudulent access to protected data through a statistical analysis of electrical currents.

Abstract translation: 为执行算法的电子电路执行的相同类型的有用操作的链接提供安全性的方法在操作的链接中随机引入一个或多个虚拟操作。 这可以通过电流的统计分析来防止对受保护数据的任何欺诈性访问。

公开(公告)号：US07187038B2

公开(公告)日：2007-03-06

申请号：US10701165

申请日：2003-11-04

Applicant: Pierre Morin ,  Jorge Luis Regolini

Inventor： Pierre Morin ,  Jorge Luis Regolini

IPC: H01L29/76 ,  H01L23/58 ,  H01L21/00 ,  H01L21/8238

CPC classification number: H01L29/7842 ,  H01L21/823814 ,  H01L21/823828 ,  H01L23/3171 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A semiconductor device includes a substrate, MOS transistors in the substrate, and a dielectric layer on the MOS transistors. Contact holes are formed through the dielectric layer to provide electrical connection to the MOS transistors. An etch-stop layer is between the MOS transistors and the dielectric layer. The etch-stop layer includes a first layer of material having a first residual stress level and covers some of the MOS transistors, and a second layer of material having a second residual stress level and covers all of the MOS transistors. The respective thickness of the first and second layers of material, and the first and second residual stress levels associated therewith are selected to obtain variations in operating parameters of the MOS transistors.

Abstract translation: 半导体器件包括衬底，衬底中的MOS晶体管和MOS晶体管上的介电层。 通过介电层形成接触孔以提供与MOS晶体管的电连接。 蚀刻停止层位于MOS晶体管和电介质层之间。 蚀刻停止层包括具有第一残余应力水平并且覆盖一些MOS晶体管的第一材料层和具有第二残余应力水平并覆盖所有MOS晶体管的第二材料层。 选择第一和第二层材料的相应厚度以及与其相关联的第一和第二残余应力水平以获得MOS晶体管的操作参数的变化。

公开(公告)号：US20070033380A1

公开(公告)日：2007-02-08

申请号：US11493865

申请日：2006-07-25

Applicant: Mathieu Lisart ,  Nicolas Demange

Inventor： Mathieu Lisart ,  Nicolas Demange

IPC: G06F15/00

CPC classification number: G06F21/556 ,  G11C7/06 ,  G11C7/1006 ,  G11C7/24

Abstract: A method processes parallel electrical signals, using parallel processing circuits that process successive cycles of electrical signals according to a rule for allocating electrical signals to the processing circuits. The method comprises, between the processing cycles, a step of modifying the rule for allocating electrical signals to the processing circuits, so that a processing circuit processes electrical signals of different ranks during different processing cycles. The method can be applied particularly to secure a memory during read phases of the memory and of an integrated circuit with a microprocessor using such a memory.

Abstract translation: 一种方法使用根据用于将电信号分配给处理电路的规则处理电信号的连续循环的并行处理电路来处理并行电信号。 该方法包括在处理周期之间，修改用于将电信号分配给处理电路的规则的步骤，使得处理电路在不同处理周期期间处理不同等级的电信号。 该方法可以特别用于在存储器的读取阶段和使用这种存储器的微处理器的集成电路中保护存储器。

公开(公告)号：US20070018735A1

公开(公告)日：2007-01-25

申请号：US11480757

申请日：2006-06-30

Applicant: Philippe Sirito-Olivier

Inventor： Philippe Sirito-Olivier

IPC: H03L7/00

CPC classification number: H03L7/10 ,  H03L7/0995 ,  H03L7/107 ,  H03L2207/06

Abstract: A phase locked loop circuit comprising a phase detector having a first input for receiving a first frequency signal and an output, a first filter adapted to filter the output electric signal of the phase detector, a voltage controlled oscillator adapted to generate a second frequency signal in response to the output filtered signal of the phase detector. The phase detector has a second input for receiving the second frequency signal and is adapted to compare it with the first frequency signal. The circuit comprises means adapted to amplify the difference between an electric signal coupled with the output of the phase detector and a reference electric signal and a second filter adapted to receive the output electric signal of the amplification means and to send an output electric signal to the voltage controlled oscillator. The circuit comprises further means adapted to modify the value of the electric signal in input to the second filter to decrease the response time of the second filter.

Abstract translation: 一种锁相环电路，包括具有用于接收第一频率信号和输出的第一输入的相位检测器，适于滤波相位检测器的输出电信号的第一滤波器，适于产生第二频率信号的压控振荡器 响应于相位检测器的输出滤波信号。 相位检测器具有用于接收第二频率信号的第二输入，并且适于将其与第一频率信号进行比较。 电路包括适于放大与相位检测器的输出耦合的电信号与参考电信号之间的差的装置，以及适于接收放大装置的输出电信号的第二滤波器，并将输出电信号发送到 压控振荡器。 该电路包括适于修改输入到第二滤波器的电信号的值以减少第二滤波器的响应时间的装置。

公开(公告)号：US07162680B2

公开(公告)日：2007-01-09

申请号：US10424166

申请日：2003-04-25

Applicant: Charaf Hanna

Inventor： Charaf Hanna

IPC: H03M13/00

CPC classification number: H03M13/2785 ,  H03M13/2707 ,  H03M13/2764

Abstract: A method for interlacing digital data to reduce transmission errors includes dividing a stream of digital data into consecutive blocks of bits, and interlacing each block of bits by writing to an interlacing table. The interlacing table is arranged in the form of rows and columns of memory addresses, with a number of the rows and columns corresponding to predetermined interlacing parameters. The access sequences to the memory addresses for interlacing the blocks of bits are different from each other. The method further includes reading a block of bits in the interlacing table according to a memory addresses access sequence, and also writing bits to a consecutive block of bits according to the memory addresses access sequence during the reading.

Abstract translation: 用于交织数字数据以减少传输错误的方法包括将数字数据流划分成连续的比特块，并且通过写入交织表来交织每个比特块。 交错表以行和列的存储器地址的形式排列，其中多个行和列对应于预定的交织参数。 到用于交错位块的存储器地址的访问序列彼此不同。 该方法还包括根据存储器地址访问序列读取交织表中的位块，并且还在读取期间根据存储器地址访问顺序将位写入连续的位块。

公开(公告)号：US20070002975A1

公开(公告)日：2007-01-04

申请号：US11428148

申请日：2006-06-30

Applicant: Jacques MEYER

Inventor： Jacques MEYER

IPC: H04L27/22 ,  H04L27/06

CPC classification number: H04L27/2273 ,  H03D3/00 ,  H04L27/22

Abstract: A process of correction of the spectral inversion for a receiver in a digital communication system: the process allows the reception in the receiver of a training sequence presumably known according to a modulation of type π/2 BPSK or MDP2. The process includes the following steps: Demodulating of the training sequence; Calculating of the differential correlation on a set of N received samples (Rn) and presumably sent (Sn) to generate a result; Using the result to detect the beginning of the frame and to order a spectral inversion in the chain of reception of the aforementioned receiver before launching the detection of the beginning of the frame. A receiver to process automatically the spectral inversion is also described.

Abstract translation: 校正数字通信系统中的接收机的频谱反演的过程：该过程允许在接收机中接收根据类型pi / 2 BPSK或MDP2的调制推测的训练序列。 该过程包括以下步骤：解调训练序列; 计算一组N个接收样本（R SUB n N）上的差分相关性，并推测发送（S N n N）以产生结果; 使用该结果来检测帧的开始，并且在开始检测帧的开始之前，在上述接收机的接收链中订购频谱反演。 还描述了自动处理频谱反演的接收机。

公开(公告)号：US07149485B2

公开(公告)日：2006-12-12

申请号：US10919796

申请日：2004-08-17

Applicant: Pierre Busson ,  Bruno Paille

Inventor： Pierre Busson ,  Bruno Paille

IPC: H04B1/18 ,  H04B1/04

CPC classification number: H04L5/06 ,  H04L27/265 ,  H04L2025/03414 ,  H04L2025/03522

Abstract: In a calibration phase for a tuner of the DZIF type, N calibration frequency signals are generated at an input of a filter. The N calibration frequency signals have N calibration frequencies corresponding respectively after transposition to N analysis frequencies at an input of a Fourier transform. An amplitude and a phase of a corresponding point at an output of the Fourier transform are calculated for each analysis frequency. In a reception phase, each of the outputs of the Fourier transform is corrected with an inverse of the corresponding amplitude and opposite the corresponding phase calculated in the calibration phase.

Abstract translation: 在DZIF型调谐器的校准阶段，N个校准频率信号在滤波器的输入端产生。 N个校准频率信号在傅立叶变换的输入处转换到N个分析频率之后分别具有N个校准频率。 对于每个分析频率计算在傅立叶变换的输出处的对应点的振幅和相位。 在接收阶段，傅立叶变换的每个输出用对应的幅度的倒数校正，与在校准阶段计算出的相应的相位相反。