公开(公告)号：US20200167327A1

公开(公告)日：2020-05-28

申请号：US16692679

申请日：2019-11-22

Applicant: Advanced Micro Devices, Inc.

Inventor： Alexander D. Breslow

IPC: G06F16/22 ,  G06F16/901 ,  G06F9/50 ,  G06N7/00

Abstract: A method of maintaining a probabilistic filter includes, in response to receiving a key K1 for adding to the probabilistic filter, generating a fingerprint F1 based on applying a fingerprint hash function HF to the key K1, identifying an initial bucket Bi1 by selecting between at least a first bucket B1 determined based on a first bucket hash function H1 of the key K1 and a second bucket B2 determined based on a second bucket hash function H2 of the key K1, and inserting the fingerprint F1 into the initial bucket Bi1; and resizing the probabilistic filter. Resizing the probabilistic filter includes incrementing a resize counter value, determining a bucket B′ for the fingerprint F1 based on a value of the fingerprint F1 and the resize counter value, and inserting the fingerprint F1 into the bucket B′ in the probabilistic filter.

公开(公告)号：US20200167291A1

公开(公告)日：2020-05-28

申请号：US16200446

申请日：2018-11-26

Applicant: ADVANCED MICRO DEVICES, INC. ,  ATI TECHNOLOGIES ULC

Inventor： Anthony ASARO ,  Richard E. GEORGE

IPC: G06F12/1009 ,  G06F11/07 ,  G06F11/36 ,  G06F9/30

Abstract: For one or more stages of execution of a software application at a first processor, a remap vector of a second processor is reconfigured to represent a dynamic mapping of virtual address groups to physical address groups for that stage. Each bit position of the remap vector is configured to store a value indicating whether a corresponding virtual address group is actively mapped to a corresponding physical address group. Address translation operations issued during a stage of execution of the software application are selectively processed based on the configuration of the remap vector for that stage, with the particular value at the bit position of the remap vector associated with the corresponding virtual address group controlling whether processing of the address translation operation is continued to obtain a virtual-to-physical address translation sought by the address translation operation or processing of the address translation operation is ceased and a fault is issued.

公开(公告)号：US20200166985A1

公开(公告)日：2020-05-28

申请号：US16210985

申请日：2018-12-05

Applicant: Advanced Micro Devices, Inc. ,  ATI Technologies ULC

Inventor： Xiaojie He ,  Alexander J. Branover ,  Mihir Shaileshbhai Doctor ,  Evgeny Mintz ,  Fei Fei ,  Ming So ,  Felix Yat-Sum Ho ,  Biao Zhou

IPC: G06F1/3293 ,  H01L23/31 ,  G06F1/324

Abstract: A computer processing device transitions among a plurality of power management states and at least one power management sub-state. From a first state, it is determined whether an entry condition for a third state is satisfied. If the entry condition for the third state is satisfied, the third state is entered. If the entry condition for the third state is not satisfied, it is determined whether an entry condition for the first sub-state is satisfied. If the entry condition for the first sub-state is determined to be satisfied, the first sub-state is entered, a first sub-state residency timer is started, and after expiry of the first sub-state residency timer, the first sub-state is exited, the first state is re-entered, and it is re-determined whether the entry condition for the third state is satisfied.

公开(公告)号：US20200158778A1

公开(公告)日：2020-05-21

申请号：US16197655

申请日：2018-11-21

Applicant: Advanced Micro Devices, Inc.

Inventor： Tan Peng ,  Dong Zhu

IPC: G01R31/317 ,  G01R31/3177 ,  G06F13/42 ,  H04L9/08

Abstract: Systems, apparatuses, and methods for implementing debug features on a secure coprocessor to handle communication and computation between a debug tool and a debug target are disclosed. A debug tool generates a graphical user interface (GUI) to display debug information to a user for help in debugging a debug target such as a system on chip (SoC). A secure coprocessor is embedded on the debug target, and the secure coprocessor receives debug requests generated by the debug tool. The secure coprocessor performs various computation tasks and/or other operations to prevent multiple round-trip messages being sent back and forth between the debug tool and the debug target. The secure coprocessor is able to access system memory and determine a status of a processor being tested even when the processor becomes unresponsive.

公开(公告)号：US10656696B1

公开(公告)日：2020-05-19

申请号：US15907719

申请日：2018-02-28

Applicant: Advanced Micro Devices, Inc. ,  ATI Technologies ULC

Inventor： Benjamin Tsien ,  Michael J. Tresidder ,  Ivan Yanfeng Wang ,  Kevin M. Lepak ,  Ann Ling ,  Richard M. Born ,  John P. Petry ,  Bryan P. Broussard ,  Eric Christopher Morton

IPC: G06F1/32 ,  G06F1/3206 ,  G06F1/3287 ,  G06F1/3234

Abstract: Systems, apparatuses, and methods for reducing chiplet interrupt latency are disclosed. A system includes one or more processing nodes, one or more memory devices, a communication fabric coupled to the processing unit(s) and memory device(s) via link interfaces, and a power management unit. The power management unit manages the power states of the various components and the link interfaces of the system. If the power management unit detects a request to wake up a given component, and the link interface to the given component is powered down, then the power management unit sends an out-of-band signal to wake up the given component in parallel with powering up the link interface. Also, when multiple link interfaces need to be powered up, the power management unit powers up the multiple link interfaces in an order which complies with voltage regulator load-step requirements while minimizing the latency of pending operations.

公开(公告)号：US20200153757A1

公开(公告)日：2020-05-14

申请号：US16188900

申请日：2018-11-13

Applicant: Advanced Micro Devices, Inc.

Inventor： Srikant Bharadwaj ,  Shomit N. Das

IPC: H04L12/933 ,  H04L12/775

Abstract: A system is described that includes an integrated circuit chip having a network-on-chip. The network-on-chip includes multiple routers arranged in a topology and a separate communication link coupled between each router and each of one or more neighboring routers of that router among the multiple routers in the topology. The integrated circuit chip also includes multiple nodes, each node coupled to a router of the multiple routers. When operating, a given router of the multiple routers keeps a record of operating states of some or all of the multiple routers and corresponding communication links. The given router then routes flits to destination nodes via one or more other routers of the multiple routers based at least in part on the operating states of the some or all of the multiple routers and the corresponding communication links.

公开(公告)号：US20200151573A1

公开(公告)日：2020-05-14

申请号：US16425403

申请日：2019-05-29

Applicant: ADVANCED MICRO DEVICES, INC.

Inventor： Shomit N. DAS ,  Abhinav VISHNU

IPC: G06N3/08 ,  G06N3/04

Abstract: A processor determines losses of samples within an input volume that is provided to a neural network during a first epoch, groups the samples into subsets based on losses, and assigns the subsets to operands in the neural network that represent the samples at different precisions. Each subset is associated with a different precision. The processor then processes the subsets in the neural network at the different precisions during the first epoch. In some cases, the samples in the subsets are used in a forward pass and a backward pass through the neural network. A memory configured to store information representing the samples in the subsets at the different precisions. In some cases, the processor stores information representing model parameters of the neural network in the memory at the different precisions of the subsets of the corresponding samples.

公开(公告)号：US20200151510A1

公开(公告)日：2020-05-14

申请号：US16424115

申请日：2019-05-28

Applicant: ADVANCED MICRO DEVICES, INC.

Inventor： Abhinav VISHNU

IPC: G06K9/62 ,  G06N3/08 ,  G06F9/38

Abstract: A method of adaptive batch reuse includes prefetching, from a CPU to a GPU, a first plurality of mini-batches comprising a subset of a training dataset. The GPU trains the neural network for the current epoch by reusing, without discard, the first plurality of mini-batches in training the neural network for the current epoch based on a reuse count value. The GPU also runs a validation set to identify a validation error for the current epoch. If the validation error for the current epoch is less than a validation error of a previous epoch, the reuse count value is incremented for a next epoch. However, if the validation error for the current epoch is greater than a validation error of a previous epoch, the reuse count value is decremented for the next epoch.

公开(公告)号：US20200151100A1

公开(公告)日：2020-05-14

申请号：US16190111

申请日：2018-11-13

Applicant: Advanced Micro Devices, Inc.

Inventor： Susumu Mashimo ,  John Kalamatianos

IPC: G06F12/0862

Abstract: A method of prefetching target data includes, in response to detecting a lock-prefixed instruction for execution in a processor, determining a predicted target memory location for the lock-prefixed instruction based on control flow information associating the lock-prefixed instruction with the predicted target memory location. Target data is prefetched from the predicted target memory location to a cache coupled with the processor, and after completion of the prefetching, the lock-prefixed instruction is executed in the processor using the prefetched target data.

公开(公告)号：US10651164B2

公开(公告)日：2020-05-12

申请号：US16591102

申请日：2019-10-02

Applicant: Advanced Micro Devices, Inc.

Inventor： Richard T. Schultz

IPC: H01L27/02 ,  H01L21/8234 ,  H01L23/528 ,  H01L23/522 ,  H01L29/423 ,  H01L27/088 ,  G06F30/392 ,  G06F30/394 ,  H01L29/66 ,  H01L29/45

Abstract: A system and method for creating layout for non-planar cells with redundancy in one or more of output contacts and power contacts are described. In various implementations, cell layout is created for a first cell with non-planar devices. An available local path in the first cell is identified for redundant output signal routing, which includes a free available metal zero layer track. Redundant metal zero layer is placed in an available metal zero track of the available local path. Redundant contacts and redundant metal one layer are placed in a free track in the available local path to connect an original output contact to a redundant output contact. An available external path is identified between the first cell and a second cell for redundant power or ground routing. One or more metal zero extension layers and/or metal one extension layers are placed in the identified external path.