公开(公告)号：US20200035685A1

公开(公告)日：2020-01-30

申请号：US16590387

申请日：2019-10-02

Applicant: UNITED MICROELECTRONICS CORP. ,  Fujian Jinhua Integrated Circuit Co., Ltd.

Inventor： Li-Wei Feng

IPC: H01L27/108 ,  H01L21/311

Abstract: A method of forming insulating structures in a semiconductor device is provided in the present invention, which includes the steps of forming a first mask layer with mandrels and a peripheral portion surrounding the mandrels, forming spacers on sidewalls of first mask layer, filling up the space between spacers with a second mask layer, removing the spacers to form opening patterns, performing an etch process with the first mask layer and the second mask layer as an etch mask to form trenches in the substrate, and filling up the trenches with an insulating material to form insulating structures.

公开(公告)号：US10535610B2

公开(公告)日：2020-01-14

申请号：US16003090

申请日：2018-06-07

Applicant: UNITED MICROELECTRONICS CORP. ,  Fujian Jinhua Integrated Circuit Co., Ltd.

Inventor： Feng-Yi Chang ,  Fu-Che Lee ,  Yi-Wang Zhan ,  Chia-Liang Liao ,  Yu-Cheng Tung ,  Chien-Hao Chen ,  Chia-Hung Wang

IPC: H01L23/544 ,  H01L27/108 ,  H01L21/311

Abstract: A semiconductor structure is disclosed. The semiconductor structure includes a substrate having a scribe line region. A material layer is formed on the scribe line region and has a rectangular region defined therein. The rectangular region has a pair of first edges parallel with a widthwise direction of the scribe line region and a pair of second edges parallel with a lengthwise direction of the scribe line region. A pair of first alignment features is formed in the material layer along the first edges, and a pair of second alignment features is formed in the material layer along the second edges. The space between the pair of first alignment features is larger than a space between the pair of the second alignment features.

公开(公告)号：US10535530B2

公开(公告)日：2020-01-14

申请号：US16167435

申请日：2018-10-22

Applicant: UNITED MICROELECTRONICS CORP. ,  Fujian Jinhua Integrated Circuit Co., Ltd.

Inventor： Feng-Yi Chang ,  Fu-Che Lee ,  Ying-Chih Lin ,  Gang-Yi Lin

IPC: H01L21/308 ,  H01L21/033 ,  H01L21/8234

Abstract: A patterning method for forming a semiconductor device is disclosed. A substrate having a hard mask disposed thereon is provided. A first patterned layer is formed on the hard mask layer. A first self-aligned double patterning process based on the first patterned layer is performed to pattern the hard mask layer into a first array pattern and a first peripheral pattern. After that, a second patterned layer is formed on the substrate. A second self-aligned double patterning process based on the second patterned layer is performed to pattern the first array pattern into a second array pattern. Subsequently, a third patterned layer is formed on the substrate. An etching process using the third patterned mask layer as an etching mask is performed to etch the first peripheral pattern thereby patterning the first peripheral pattern into a second peripheral pattern.

公开(公告)号：US20200013724A1

公开(公告)日：2020-01-09

申请号：US16049826

申请日：2018-07-31

Applicant: UNITED MICROELECTRONICS CORP. ,  Fujian Jinhua Integrated Circuit Co., Ltd.

Inventor： Zheng-Feng Chen ,  Sho-Shen Lee ,  En-Chiuan Liou ,  Hsiao-Lin Hsu ,  Yi-Ting Chen ,  Lu-Wei Kuo

IPC: H01L23/544 ,  H01L27/108 ,  H01L21/027 ,  H01L21/311 ,  H01L21/3213

Abstract: A method of forming an overlay mark structure includes the following steps. An insulation layer is formed on a substrate. A first overlay mark is formed in the insulation layer. A metal layer is formed on the substrate. The metal layer covers the insulation layer and the first overlay mark. The metal layer on the first overlay mark is removed. A top surface of the first overlay mark is lower than a top surface of the insulation layer after the step of removing the metal layer on the first overlay mark. A second overlay mark is formed on the metal layer. In the method of forming the overlay mark structure, the first overlay mark may not be covered by the metal layer for avoiding influences on related measurements, and the second overlay mark may be formed on the metal layer for avoiding related defects generated by the height difference.

公开(公告)号：US10529854B1

公开(公告)日：2020-01-07

申请号：US16109714

申请日：2018-08-22

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Purakh Raj Verma ,  Chih-Wei Su ,  Je-Min Wen

IPC: H01L29/78 ,  H01L29/786 ,  H01L21/764 ,  H01L29/66 ,  H01L21/311 ,  H01L29/06 ,  H01L21/762

Abstract: A method for fabricating semiconductor device includes the steps of: providing a substrate having a first silicon layer, an insulating layer on the first silicon layer, and a second silicon layer on the insulating layer; forming a metal-oxide semiconductor (MOS) transistor on the substrate; forming an interlayer dielectric layer (ILD) on the MOS transistor; removing part of the ILD layer to form a first trench to expose the insulating layer; and performing a wet etching process through the first trench to remove part of the insulating layer for forming a first air gap under the MOS transistor.

公开(公告)号：US10529723B2

公开(公告)日：2020-01-07

申请号：US15186548

申请日：2016-06-20

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Shu-Wei Yeh ,  Tsung-Hsun Wu ,  Chih-Ming Su ,  Yu-Tse Kuo

IPC: H01L27/11 ,  H01L27/02

Abstract: A layout pattern of a static random access memory includes a pull-up device, a first pull-down device, a second pull-up device, a second pull-down device, a first pass gate device and a second pass gate device disposed on a substrate. A plurality of fin structures are disposed on the substrate, and the fin structures include at least one first fin structure and at least one second fin structure. A J-shaped gate structure is disposed on the substrate, including a long part, a short part and a bridge part. At least one first extending contact structure crosses over the at least one first fin structure and the at least one second fin structure, wherein the at least one first extending contact structure does not overlap with the bridge part of the J-shaped gate structure.

公开(公告)号：US10529715B2

公开(公告)日：2020-01-07

申请号：US15427512

申请日：2017-02-08

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Wei-Lun Hsu ,  Yung-Chien Kung ,  Ming-Tsung Yeh ,  Yan-Hsiu Liu ,  Am-Tay Luy ,  Yao-Pi Hsu ,  Ji-Fu Kung

IPC: H01L21/304 ,  H01L27/092 ,  H01L21/762 ,  H01L21/8238 ,  H01L21/761 ,  H01L21/8234 ,  H01L29/78

Abstract: An integrated circuit (IC) structure includes a substrate having several regions, several semiconductor devices formed at the substrate and respectively within the regions, and an ultra-deep (UD) trench isolation structure formed in the substrate. The substrate has a top surface and a bottom surface oppositely, and the UD trench isolation structure formed in the substrate surrounds peripheries of each of the regions for structurally and physically isolating the semiconductor devices within different regions. The UD trench isolation structure penetrates the substrate by extending from the top surface of the substrate to the bottom surface of the substrate.

公开(公告)号：US10529707B2

公开(公告)日：2020-01-07

申请号：US15983096

申请日：2018-05-18

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Hsin-Hsien Chen ,  Sheng-Yuan Hsueh ,  Yi-Chung Sheng ,  Chih-Kai Kang ,  Wen-Kai Lin ,  Shu-Hung Yu

IPC: H01L27/06 ,  H01L21/768 ,  H01L29/06 ,  H01L49/02 ,  H01L23/528

Abstract: A method of forming a capacitor includes the following steps. First, a substrate is provided. A dielectric layer is formed over the substrate. A first patterning process is performed to form a first contact plug through the whole thickness of the dielectric layer and a second patterning process is performed to form a second contact plug in the dielectric layer and spaced apart from the first contact plug in a pre-determined distance, wherein the first contact plug and the second contact plug are capacitively coupled.

公开(公告)号：US10529423B2

公开(公告)日：2020-01-07

申请号：US16438485

申请日：2019-06-12

Applicant: UNITED MICROELECTRONICS CORP. ,  Fujian Jinhua Integrated Circuit Co., Ltd.

Inventor： Yukihiro Nagai

IPC: G11C14/00 ,  G11C29/00 ,  H01L27/11573 ,  H01L21/311 ,  H01L21/28 ,  H01L21/3213 ,  H01L29/49 ,  H01L29/66 ,  H01L27/108 ,  H01L29/792 ,  G11C11/401 ,  H01L29/51 ,  G11C16/04

Abstract: A DRAM device with embedded flash memory for redundancy is disclosed. The DRAM device includes a substrate having a DRAM array area and a peripheral area. The peripheral area includes an embedded flash forming region and a first transistor forming region. DRAM cells are disposed within the DRAM array area. Flash memory is disposed in the embedded flash forming region. The flash memory includes an ONO storage structure and a flash memory gate structure. A first transistor is disposed in the first transistor forming region.

公开(公告)号：US20200006519A1

公开(公告)日：2020-01-02

申请号：US16054963

申请日：2018-08-03

Applicant: United Microelectronics Corp.

Inventor： Purakh Raj Verma ,  Kuo-Yuh Yang

IPC: H01L29/66 ,  H01L29/06 ,  H01L27/12 ,  H01L21/768

Abstract: A semiconductor structure including a substrate, a complementary metal oxide semiconductor (CMOS) device and a bipolar junction transistor (BJT) is provided. The CMOS device includes an N-type metal oxide semiconductor (NMOS) transistor and a P-type metal oxide semiconductor (PMOS) transistor disposed on the substrate. The BJT includes a collector, a base and an emitter. The collector is disposed in the substrate. The base is disposed on the substrate. The emitter is disposed on the base. A top surface of a channel of the NMOS transistor, a top surface of a channel of the PMOS transistor and a top surface of the collector of the BJT have the same height. The semiconductor structure can have better overall performance.