公开(公告)号：US5629574A

公开(公告)日：1997-05-13

申请号：US86170

申请日：1993-06-30

Applicant: Carlo Cognetti ,  Giuseppe Marchisi

Inventor： Carlo Cognetti ,  Giuseppe Marchisi

IPC: H02K5/22 ,  H02K11/04 ,  H02K23/66 ,  H02K11/00 ,  H01L23/28 ,  H02K1/04 ,  H02K15/00

CPC classification number: H02K5/225 ,  H02K11/33 ,  H02K23/66 ,  H01L2924/0002 ,  H02K2211/03

Abstract: A control interface device for an electric motor, particularly an electric motor for operating servomechanisms on a vehicle, which includes a conductor frame, an active integrated component mounted on the conductor frame, and a plurality of electric connectors. A single insulating, one-piece enclosing body contains the conductor frame with the active integrated component and the electric connectors included to the conductor frame. Thus, all of the elements required for powering and controlling the motor are gathered inside a single enclosing body which is convenient to handle and connect.

Abstract translation: 一种用于电动机的控制接口装置，特别是用于在车辆上操作伺服机构的电动机，其包括导体框架，安装在导体框架上的有源集成部件和多个电连接器。 单个绝缘的一体封闭体包含具有有源集成部件的导体框架和包括在导体框架中的电连接器。 因此，电动机控制所需的所有元件都集中在一个容易处理和连接的封闭体内。

公开(公告)号：USRE35494E

公开(公告)日：1997-04-22

申请号：US236673

申请日：1994-05-02

Applicant: Germano Nicollini

Inventor： Germano Nicollini

IPC: H03H19/00 ,  H03B1/00 ,  H03K5/00

CPC classification number: H03H19/004

Abstract: An integrated, low-pass filter of the first order made using the switched capacitors technique utilizes advantageously a single switched capacitor and only two switches in contrast to the filters of the prior art which utilize two switched capacitors and four switches. The filter of the invention requires a smaller integration area and moreover exhibits a greater precision of its DC gain.

Abstract translation: 使用开关电容器技术制成的第一级的集成低通滤波器有利地利用单个开关电容器，并且仅使用两个开关，与使用两个开关电容器和四个开关的现有技术的滤波器相反。 本发明的滤波器需要较小的积分面积，并且还具有更高的DC增益精度。

公开(公告)号：US5623254A

公开(公告)日：1997-04-22

申请号：US367746

申请日：1995-01-03

Applicant: Massimiliano Brambilla ,  Giampietro Maggioni

Inventor： Massimiliano Brambilla ,  Giampietro Maggioni

IPC: G01R31/02 ,  H03K17/082 ,  B60Q1/00

CPC classification number: G01R31/024 ,  H03K17/0822

Abstract: A drive circuit fault detection device comprising a discriminating circuit generating a digital signal, the level of which indicates a fault; and an identifying circuit generating a binary-coded signal indicating the type of fault, i.e. ground shorting of the drive circuit or an open load. The discriminating circuit comprises a resistive network connected to the output of the drive circuit, for generating a voltage indicating correct connection of the load or a fault on the drive circuit and a comparator for comparing the generated voltage with a reference voltage and supplying the digital signal at its output. The identifying circuit comprises a current mirror circuit generating an output voltage having two different logic levels in the event of short circuiting or an open load, respectively, and a combination circuit for generating the binary-coded output signal.

Abstract translation: 一种驱动电路故障检测装置，包括产生数字信号的识别电路，其电平表示故障; 以及识别电路，产生指示故障类型的二进制编码信号，即驱动电路的接地短路或开路负载。 识别电路包括连接到驱动电路的输出的电阻网络，用于产生指示驱动电路上的负载或故障的正确连接的电压以及比较器，用于将产生的电压与参考电压进行比较并提供数字信号 在其产出。 识别电路包括分别在短路或开路负载的情况下产生具有两个不同逻辑电平的输出电压的电流镜电路和用于产生二进制编码的输出信号的组合电路。

公开(公告)号：US5617295A

公开(公告)日：1997-04-01

申请号：US414285

申请日：1995-03-31

Applicant: Renato Poinelli ,  Mauro Mazzola ,  Paolo Casati

Inventor： Renato Poinelli ,  Mauro Mazzola ,  Paolo Casati

IPC: H01L23/28 ,  H01L23/433 ,  H01L23/495 ,  H01L23/50 ,  H05K7/20

CPC classification number: H01L23/4334 ,  H01L23/49582 ,  H01L2224/05554 ,  H01L2224/45144 ,  H01L2224/48091 ,  H01L24/45 ,  H01L2924/14

Abstract: A leadframe for electronic semiconductor devices incorporates one or two metal bars fastened to a heat dissipator by electroconductive means.Each bar has a metallized area for the electric connection, by means of a bonding wire, with a semiconductor chip placed on the dissipator.According to the present invention, the metallized areas are lowered in relation to the upper surface of the metal bar, so that lead frames can be stacked, during packing and transportation, directly on each other without danger of damaging the metallized areas.

Abstract translation: 用于电子半导体器件的引线框架包括通过导电装置固定到散热器的一个或两个金属条。 每个棒具有用于电连接的金属化区域，借助于接合线，半导体芯片放置在耗散器上。 根据本发明，金属化区域相对于金属棒的上表面降低，使得引线框架可以在包装和运输期间彼此直接堆叠而不会损坏金属化区域。

公开(公告)号：US5612610A

公开(公告)日：1997-03-18

申请号：US328232

申请日：1994-10-24

Applicant: Maria R. Borghi ,  Pietro Menniti

Inventor： Maria R. Borghi ,  Pietro Menniti

IPC: H02M3/155 ,  G05F1/614 ,  H02M3/156 ,  G05F1/613

CPC classification number: H02M3/1563 ,  G05F1/614

Abstract: A converter employs a comparator sensing the current through an output diode, for generating a confirmation signal of an OFF state of the switch until the discharge current of the inductor toward the user circuit and the external filter capacitance has become null, thus ensuring the operation in a discontinuous mode under any condition. A turn-off signal of the switch is provided by another comparator which, instead of the voltage on a sensing resistance connected in series with the switch, may sense the voltage across the switch itself. This latter embodiment is particularly suited in case of an output MOS transistor and the circuit comprises means for masking for a preset period of time the turn-off signal produced by said comparator, in order to allow a predefined turn-on phase of the switch. Enabling of the turn-on of the switch is conventionally provided by a dedicated (third) comparator of the output voltage. The circuit does not require the use of an error amplifier, for the compensation of which special complex integratable circuits or alternatively access to the output node of the error amplifier through a dedicated pin may be needed. Neither a local oscillator for turning off the switch is needed. The circuit is simple and suited for integration in large complex system chips, where there is a limited availability of pins and silicon area. Different embodiments are described.

Abstract translation: A转换器采用比较器来感测通过输出二极管的电流，用于产生开关的OFF状态的确认信号，直到电感器朝向用户电路的放电电流和外部滤波电容变为零，从而确保在 任何条件下的不连续模式。 开关的关断信号由另一比较器提供，该比较器代替与开关串联连接的感测电阻上的电压可以感测开关本身两端的电压。 后一个实施例特别适用于输出MOS晶体管的情况，并且电路包括用于在预设时间段内屏蔽由所述比较器产生的关断信号的装置，以便允许开关的预定的接通阶段。 开关的导通通常由输出电压的专用（第三）比较器提供。 电路不需要使用误差放大器，用于补偿哪些特殊的复合可积分电路，或者可能需要通过专用引脚访问误差放大器的输出节点。 不需要用于关闭开关的本地振荡器。 该电路简单，适用于集成在大型复杂系统芯片中，其中引脚和硅面积有限。 描述不同的实施例。

公开(公告)号：US5606625A

公开(公告)日：1997-02-25

申请号：US249316

申请日：1994-05-26

Applicant: Carlo Dallavalle ,  Carlo Crippa ,  Pierangelo Confalonieri

Inventor： Carlo Dallavalle ,  Carlo Crippa ,  Pierangelo Confalonieri

IPC: H03G3/20 ,  H03G3/30 ,  H03G5/16 ,  H03G3/00

CPC classification number: H03G3/3089

Abstract: A digital circuit for controlling the gain of an amplifier stage of a coded signal receiving channel is provided. The circuit includes a peak detector coupled to the input terminal of the receiving channel through a coded signal rectifying circuit and a gain control stage. The gain control stage includes a digital comparator having two input terminals respectively connected to an output terminal of the peak detector and to a memory, and an output terminal coupled to a gain control terminal of the amplifier stage. The address selectable contents of the memory contain predetermined peak values in coded form.

Abstract translation: 提供了一种用于控制编码信号接收通道的放大器级的增益的数字电路。 电路包括通过编码信号整流电路和增益控制级耦合到接收信道的输入端的峰值检测器。 增益控制级包括数字比较器，其具有分别连接到峰值检测器的输出端子和存储器的两个输入端子，以及耦合到放大器级的增益控制端子的输出端子。 存储器的地址可选择内容包含编码形式的预定峰值。

公开(公告)号：US5600166A

公开(公告)日：1997-02-04

申请号：US457514

申请日：1995-06-01

Applicant: Cesare Clementi ,  Gabriella Ghidini ,  Marina Tosi

Inventor： Cesare Clementi ,  Gabriella Ghidini ,  Marina Tosi

IPC: G11C17/00 ,  H01L21/8247 ,  H01L27/115 ,  H01L29/51 ,  H01L29/788 ,  H01L29/792

CPC classification number: H01L29/511 ,  Y10S148/114

Abstract: The use of an O--N--RTN (Oxide-Nitride-Rapid Thermal Nitrided Polysilicon) interpoly dielectric multilayer instead of a customary O--N--O (Oxide-Nitride-Oxide) multilayer in the floating gate structure of a progammable, read-only memory cell has beneficial effects on the performance of the cell and facilitates its scaling.

Abstract translation: 使用ON-RTN（氧化氮 - 氮化物 - 快速热氮化多晶硅）多层电介质多层而不是常规的ONO（氧化物 - 氮化物 - 氧化物）多层在可执行的只读存储器单元的浮动栅极结构中具有有益的效果 关于电池的性能，并促进其缩放。

公开(公告)号：US5595921A

公开(公告)日：1997-01-21

申请号：US459052

申请日：1995-06-02

Applicant: Flavio Villa ,  Enrico M. A. Ravanelli

Inventor： Flavio Villa ,  Enrico M. A. Ravanelli

IPC: H01L21/336 ,  H01L29/10 ,  H01L29/78 ,  H01L21/8234

CPC classification number: H01L29/7816 ,  H01L29/1083 ,  H01L29/66659 ,  H01L29/7801 ,  H01L29/0878 ,  Y10S148/126

Abstract: The breakdown characteristics of a lateral transistor integrated in an epitaxial layer of a first type of conductivity grown on a substrate of an opposite type of conductivity and comprising a drain region formed in said epitaxial layer, are markedly improved without recurring to critical adjustments of physical parameters of the integrated structure by forming a buried region having the same type of conductivity of the substrate and a slightly higher level of doping at the interface between the epitaxial layer and the substrate in a zone laying beneath the drain region of the transistor.

Abstract translation: 集成在具有相反导电性的衬底上生长并且包括形成在所述外延层中的漏极区的第一类型导电体的外延层中的横向晶体管的击穿特性显着改善，而不会重复进行物理参数的临界调整 通过形成具有相同类型的衬底的导电性的掩埋区域和在位于晶体管的漏极区域下方的区域中在外延层和衬底之间的界面处稍微更高的掺杂水平的一体结构。

公开(公告)号：US5594677A

公开(公告)日：1997-01-14

申请号：US189271

申请日：1994-01-28

Applicant: Carla Golla ,  Alessandro Cremonesi

Inventor： Carla Golla ,  Alessandro Cremonesi

IPC: H03H21/00 ,  G06F17/10 ,  H03H17/00 ,  H03H17/02 ,  H03H17/06 ,  H04B3/04

CPC classification number: H03H17/0286 ,  H03H17/02 ,  H03H2017/0247

Abstract: The input signal is filtered using at least two filtering operations (i.e. at least two types of transfer functions), and then is reconstituted by summing the two different digital outputs generated by each filtering arrangement, for example by using a summing circuit. In a preferred embodiment of the invention, a single programmable filter processor is used and is operated in two alternately selected modes, each sharing common filter coefficients. A clock signal alternately selects the two filtering modes. The subsequent outputs from a first mode are delayed and then added to the output of the second mode to produce the desired output signal.

Abstract translation: 使用至少两个滤波操作（即至少两种传递函数）对输入信号进行滤波，然后通过例如通过使用求和电路对由每个滤波装置产生的两个不同的数字输出相加来进行重构。 在本发明的优选实施例中，使用单个可编程滤波器处理器并且以两个交替选择的模式操作，每个模式共享共同的滤波器系数。 时钟信号交替选择两种滤波模式。 来自第一模式的后续输出被延迟，然后被添加到第二模式的输出以产生期望的输出信号。

公开(公告)号：US5592485A

公开(公告)日：1997-01-07

申请号：US876127

申请日：1992-04-29

Applicant: Franco Consiglieri ,  Arturo Wolfsgruber ,  Sandro Storti

Inventor： Franco Consiglieri ,  Arturo Wolfsgruber ,  Sandro Storti

IPC: B60R16/02 ,  B60R16/023 ,  B60R16/03 ,  G05B19/00

CPC classification number: B60R16/0315 ,  B60R2016/0322

Abstract: A connection system of the multiplex type between at least one master processing unit and slave units, in particular associated with electrical devices in a vehicle for activating or controlling at least one electrically functioning component in the corresponding device, the slave units being connected in groups to the master unit by means of corresponding communication channels common to the units of each group, and in which the master unit includes logical means for controlling the exchange of communications between the various channels; in particular these logical means include a microprocessor and control corresponding first blocks enabling transmission on such communication channels and corresponding second blocks enabling communication between the abovementioned channels.

Abstract translation: 一种在至少一个主处理单元和从单元之间的多路复用类型的连接系统，特别是与车辆中的电气设备相关联，用于激活或控制相应设备中的至少一个电功能部件，从属单元分组连接 所述主单元借助于每个组的单元共同的相应通信信道，并且其中主单元包括用于控制各个信道之间的通信交换的逻辑装置; 特别地，这些逻辑装置包括微处理器和控制对应的第一块，使得能够在这种通信信道上进行传输，并且相应的第二块能够实现上述信道之间的通信。