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    Integrated mechanical device for electrical switching
    601.
    发明授权
    Integrated mechanical device for electrical switching 有权
    集成电气开关机械装置

    公开(公告)号：US08692247B2

    公开(公告)日：2014-04-08

    申请号：US13687932

    申请日：2012-11-28

    Applicant: STMicroelectronics (Rousset) SAS

    Inventor： Pascal Fornara ,  Christian Rivero ,  Antonio di-Giacomo

    IPC: H01L23/58

    CPC classification number: H01H37/52 ,  B81B3/0024 ,  G01K3/005 ,  G01K5/486 ,  H01L23/58 ,  H01L2924/0002 ,  H01L2924/00

    Abstract: An integrated circuit comprising a mechanical device for electrical switching comprising a first assembly being thermally deformable and having a beam held at at least two different locations by at least two arms, the beam and the arms being metal and disposed within the same metallization level, and further comprising at least one electrically conducting body. The first assembly has a first configuration at a first temperature and a second configuration at a second temperature different from the first temperature. The beam is out of contact with the electrically conducting body in one configuration in contact with the body in the other configuration. The beam establishes or breaks an electrical link passing through the said at least one electrically conducting body and through the said beam in the different configurations.

    Abstract translation: 一种集成电路，包括用于电开关的机械装置，包括可热变形的第一组件，并且具有通过至少两个臂保持在至少两个不同位置处的梁，所述梁和所述臂是金属并且设置在相同的金属化水平内，以及 还包括至少一个导电体。 第一组件具有在第一温度下的第一构型和在与第一温度不同的第二温度下的第二构型。 在与另一种结构中的身体接触的一种结构中，光束与导电体脱离接触。 光束建立或断开通过所述至少一个导电体并通过所述光束的不同构造的电连接。

    Method for Managing the Operation of a Circuit Connected to a Two-Wire Bus
    602.
    发明申请
    Method for Managing the Operation of a Circuit Connected to a Two-Wire Bus 有权
    管理连接到两线总线的电路的操作方法

    公开(公告)号：US20140095750A1

    公开(公告)日：2014-04-03

    申请号：US14042344

    申请日：2013-09-30

    Applicant: STMicroelectronics Rousset) SAS

    Inventor： Francois Tailliet

    IPC: G06F13/42

    CPC classification number: G06F13/4282 ,  G06F13/4077

    Abstract: A method is provided for managing the operation of a circuit operating in a slave mode. The circuit is connected to a bus having at least two of wires and a priority logic level. The slave circuit imposes the priority logic level on a first wire of the bus. While imposing, the slave circuit detects a possible conflict on the first wire resulting from a forcing, external to the slave circuit, of the first wire to another logic level. Upon detecting a conflict, the slave circuit is placed in a state stopping the sending by the circuit of any data over the bus while leaving the circuit listening to the bus.

    Abstract translation: 提供了一种用于管理在从模式下操作的电路的操作的方法。 电路连接到具有至少两根导线和优先级逻辑电平的总线。 从电路在总线的第一根线上施加优先级逻辑电平。 在施加时，从电路检测到第一线上的强制（从属电路外部）将第一导线的第一导线的可能冲突与第一导线的另一逻辑电平相冲突。 在检测到冲突时，从电路处于停止通过总线发送任何数据的状态，同时让电路监听总线。

    Electronic Device for Protecting Against a Polarity Reversal of a DC Power Supply Voltage, and its Application to Motor Vehicles
    603.
    发明申请
    Electronic Device for Protecting Against a Polarity Reversal of a DC Power Supply Voltage, and its Application to Motor Vehicles 审中-公开
    用于防止直流电源电压极性反转的电子装置及其在机动车辆上的应用

    公开(公告)号：US20140029146A1

    公开(公告)日：2014-01-30

    申请号：US14041654

    申请日：2013-09-30

    Applicant: STMicroelectronics (Rousset) SAS

    Inventor： Antoine Pavlin

    IPC: H02H3/18

    CPC classification number: H02H3/18 ,  H01L27/0248 ,  H01L27/0251 ,  H01L27/088 ,  H02H11/003

    Abstract: Disclosed herein is a device comprising a protection circuit configured to protect against a polarity reversal of the input DC power supply voltage, the protection circuit comprising an N-channel main transistor having a source coupled to an input terminal and having a drain coupled to an output terminal, a command circuit configured to render the main transistor blocked in the event of a polarity reversal and conducting otherwise, and a control circuit configured to dynamically adjust the bias of substrate regions of respective components connected to the main transistor by connecting the substrate regions either to the source or to the drain of the main transistor according to the value of the voltages present at the source and the drain of the main transistor and the type of conductivity of the substrate regions.

    Abstract translation: 本文公开了一种包括保护电路的装置，其被配置为防止输入DC电源电压的极性反转，该保护电路包括N沟道主晶体管，其具有耦合到输入端子的源极，并且具有耦合到输出的漏极 端子，命令电路，其被配置为在极性反转的情况下使主晶体管阻塞并且否则导通;以及控制电路，被配置为通过将衬底区域连接来动态地调节连接到主晶体管的各个部件的衬底区域的偏置 根据存在于主晶体管的源极和漏极上的电压值以及衬底区域的导电类型，到主晶体管的源极或漏极。

    METHOD OF COMPENSATING FOR EFFECTS OF MECHANICAL STRESSES IN A MICROCIRCUIT
    604.
    发明申请
    METHOD OF COMPENSATING FOR EFFECTS OF MECHANICAL STRESSES IN A MICROCIRCUIT 有权
    补偿机械应力在微型计算机中的影响的方法

    公开(公告)号：US20140026670A1

    公开(公告)日：2014-01-30

    申请号：US13953571

    申请日：2013-07-29

    Applicant: STMicroelectronics (Rousset) SAS

    Inventor： Pascal Fornara ,  Christian Rivero

    IPC: G01L1/00 ,  H01L29/66

    CPC classification number: G01R31/2872 ,  G01L1/00 ,  G01L1/005 ,  G01L1/148 ,  G01L1/225 ,  G01L1/2293 ,  G01L11/00 ,  G01L25/00 ,  G01R31/2884 ,  H01L27/06 ,  H01L29/66007

    Abstract: A method for manufacturing an integrated circuit includes forming in a substrate a measuring circuit sensitive to mechanical stresses and configured to supply a measurement signal representative of mechanical stresses exerted on the measuring circuit. The measuring circuit is positioned such that the measurement signal is also representative of mechanical stresses exerted on a functional circuit of the integrated circuit. A method of using the integrated circuit includes determining from the measurement signal the value of a parameter of the functional circuit predicted to mitigate an impact of the variation in mechanical stresses on the operation of the functional circuit, and supplying the functional circuit with the determined value of the parameter.

    Abstract translation: 一种用于制造集成电路的方法包括在基板上形成对机械应力敏感的测量电路，并且被配置为提供表示施加在测量电路上的机械应力的测量信号。 测量电路被定位成使得测量信号也代表施加在集成电路的功能电路上的机械应力。 使用集成电路的方法包括从测量信号确定预测的功能电路的参数的值，以减轻机械应力的变化对功能电路的操作的影响，以及向功能电路提供确定的值 的参数。

    Method for Detecting Electrical Energy Produced from a Thermoelectric Material contained in an Integrated Circuit
    605.
    发明申请
    Method for Detecting Electrical Energy Produced from a Thermoelectric Material contained in an Integrated Circuit 审中-公开
    用于检测集成电路中包含的热电材料产生的电能的方法

    公开(公告)号：US20130314150A1

    公开(公告)日：2013-11-28

    申请号：US13959496

    申请日：2013-08-05

    Applicant: STMicroelectronics (Rousset) SAS

    Inventor： Pascal Fornara ,  Christian Rivero

    IPC: H01L23/00

    CPC classification number: H01L23/576 ,  H01L2924/0002 ,  H01L2924/00

    Abstract: An integrated circuit includes active circuitry disposed at a surface of a semiconductor body and an interconnect region disposed above the semiconductor body. A thermoelectric material is disposed in an upper portion of the interconnect region away from the semiconductor body. The thermoelectric material is configured to deliver electrical energy when exposed to a temperature gradient. This material can be used, for example, in a method for detecting the repackaging of the integrated circuit after it has been originally packaged.

    Abstract translation: 集成电路包括设置在半导体主体的表面的有源电路和设置在半导体主体上方的互连区域。 热电材料设置在互连区域的远离半导体本体的上部。 热电材料被配置为当暴露于温度梯度时传递电能。 该材料可以用于例如在最初封装集成电路的重新包装检测方法之后。

    NONVOLATILE MEMORY CELLS WITH A VERTICAL SELECTION GATE OF VARIABLE DEPTH
    608.
    发明申请
    NONVOLATILE MEMORY CELLS WITH A VERTICAL SELECTION GATE OF VARIABLE DEPTH 有权
    具有可变深度的垂直选择门的非易失性记忆细胞

    公开(公告)号：US20130228846A1

    公开(公告)日：2013-09-05

    申请号：US13786213

    申请日：2013-03-05

    Applicant: STMICROELECTRONICS (ROUSSET) SAS

    Inventor： Francesco LA ROSA ,  Yoann GOASDUFF ,  Stephan NIEL ,  Arnaud REGNIER

    IPC: H01L29/788 ,  H01L29/66

    CPC classification number: H01L29/7889 ,  G11C16/0425 ,  G11C16/0483 ,  G11C16/14 ,  H01L27/11524 ,  H01L29/66825

    Abstract: The disclosure relates to an integrated circuit comprising at least two memory cells formed in a semiconductor substrate, and a buried gate common to the selection transistors of the memory cells. The buried gate has a first section of a first depth extending in front of vertical channel regions of the selection transistors, and at least a second section of a second depth greater than the first depth penetrating into a buried source line. The lower side of the buried gate is bordered by a doped region forming a source region of the selection transistors and reaching the buried source line at the level where the second section of the buried gate penetrates into the buried source line, whereby the source region is coupled to the buried source line.

    Abstract translation: 本公开涉及一种集成电路，其包括形成在半导体衬底中的至少两个存储单元和与存储单元的选择晶体管共同的掩埋栅极。 掩埋栅极具有在选择晶体管的垂直沟道区域的前面延伸的第一深度的第一部分，以及大于深入埋入源极线的第一深度的至少第二深度的第二部分。 掩埋栅极的下侧由形成选择晶体管的源极区域的掺杂区域界定，并且在埋入栅极的第二部分穿入埋入源极线的水平面到达掩埋源极线，由此源极区域 耦合到埋地源线。

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