公开(公告)号：US20200073669A1

公开(公告)日：2020-03-05

申请号：US16116666

申请日：2018-08-29

Applicant: ADVANCED MICRO DEVICES, INC.

Inventor： Thomas CLOUQUEUR

IPC: G06F9/38

Abstract: A processing system includes a processor with a branch predictor including one or more branch target buffer tables. The processor also includes a branch prediction pipeline including a throttle unit and an uncertainty accumulator. The processor assigns an uncertainty value for each of a plurality of branch predictions generated by the branch predictor and adds the uncertainty value for each of the plurality of branch predictions to an accumulated uncertainty counter associated with the uncertainty accumulator. The throttle unit of the branch prediction pipeline throttles operations of the branch prediction pipeline based on the accumulated uncertainty counter.

公开(公告)号：US10581587B1

公开(公告)日：2020-03-03

申请号：US16397848

申请日：2019-04-29

Applicant: Advanced Micro Devices, Inc. ,  ATI Technologies ULC

Inventor： Varun Gupta ,  Milam Paraschou ,  Gerald R. Talbot ,  Gurunath Dollin ,  Damon Tohidi ,  Eric Ian Carpenter ,  Chad S. Gallun ,  Jeffrey Cooper ,  Hanwoo Cho ,  Thomas H. Likens, III ,  Scott F. Dow ,  Michael J. Tresidder

IPC: H04B17/00 ,  H04L7/04 ,  H04L7/00

Abstract: Systems, apparatuses, and methods for implementing a deskewing method for a physical layer interface on a multi-chip module are disclosed. A circuit connected to a plurality of communication lanes trains each lane to synchronize a local clock of the lane with a corresponding global clock at a beginning of a timing window. Next, the circuit symbol rotates each lane by a single step responsive to determining that all of the plurality of lanes have an incorrect symbol alignment. Responsive to determining that some but not all of the plurality of lanes have a correct symbol alignment, the circuit symbol rotates lanes which have an incorrect symbol alignment by a single step. When the end of the timing window has been reached, the circuit symbol rotates lanes which have a correct symbol alignment and adjusts a phase of a corresponding global clock to compensate for missed symbol rotations.

公开(公告)号：US10579557B2

公开(公告)日：2020-03-03

申请号：US15872943

申请日：2018-01-16

Applicant: Advanced Micro Devices, Inc.

Inventor： Nuwan Jayasena ,  Michael Ignatowski

IPC: G06F13/16 ,  G06F3/06

Abstract: A configurable computing system which uses near-memory and in-memory hardened logic blocks is described herein. The hardened logic blocks are incorporated into memory modules. The memory modules include an interface or communication logic to communicate between the configurable computing substrate and the memory module. In an implementation, the memory modules can include an on-die memory or other forms of non-configurable logic to enable more efficient processing for a variety of operations. In another implementation, the memory modules can include a portion of configurable computing substrate logic fabric to enable more efficient processing for a variety of operations. In another implementation, the memory modules can include an on-die memory and a portion of configurable computing substrate logic fabric to enable more efficient processing for a variety of operations.

公开(公告)号：US20200065255A1

公开(公告)日：2020-02-27

申请号：US16110062

申请日：2018-08-23

Applicant: Advanced Micro Devices, Inc.

Inventor： MICHAEL W. LEBEANE ,  SEUNGHEE SHIN

IPC: G06F12/10

Abstract: An apparatus and method performs neighborhood-aware virtual to physical address translations. A coalescing opportunity for a first virtual address is determined, based on completing a memory access corresponding to a page walk for a second virtual address. Metadata corresponding to the first virtual address is provided to a page table walk buffer based on the coalescing opportunity and a page walk for the first virtual address is performed based on the metadata corresponding to the first virtual address.

公开(公告)号：US10560022B2

公开(公告)日：2020-02-11

申请号：US16440838

申请日：2019-06-13

Applicant: Advanced Micro Devices, Inc.

Inventor： Wei Huang ,  Miguel Rodriguez ,  Karthik Rao

IPC: H02M3/158 ,  G05F1/575 ,  G05F1/46 ,  G05F1/56 ,  H02M1/00

Abstract: An apparatus includes an integrated circuit chip with a set of circuits having two or more subsets of circuits; an external voltage regulator separate from the integrated circuit chip; two or more integrated voltage regulators on the integrated circuit chip that each provide an input voltage to a respective subset of the circuits; and a controller. The controller determines, using an integrated voltage regulator power loss model, an electrical power loss for the integrated voltage regulators for a first combination of operating points for the subsets of the circuits. The controller then determines, based on the electrical power loss, a second combination of operating points for the subsets of the circuits that includes an adjustment to an operating point for at least one of the subsets of the circuits that compensates for an electrical power loss of the corresponding integrated voltage regulator. The controller sets an operating point of each of the subsets of the circuits based on the second combination of operating points.

公开(公告)号：US20200042348A1

公开(公告)日：2020-02-06

申请号：US16050948

申请日：2018-07-31

Applicant: Advanced Micro Devices, Inc. ,  ATI Technologies ULC

Inventor： Anirudh R. Acharya ,  Michael J. Mantor ,  Rex Eldon McCrary ,  Anthony Asaro ,  Jeffrey Gongxian Cheng ,  Mark Fowler

IPC: G06F9/48 ,  G06F12/1009 ,  G06F12/14 ,  G06F9/52 ,  G06F9/54 ,  G06T1/20

Abstract: Systems, apparatuses, and methods for abstracting tasks in virtual memory identifier (VMID) containers are disclosed. A processor coupled to a memory executes a plurality of concurrent tasks including a first task. Responsive to detecting one or more instructions of the first task which correspond to a first operation, the processor retrieves a first identifier (ID) which is used to uniquely identify the first task, wherein the first ID is transparent to the first task. Then, the processor maps the first ID to a second ID and/or a third ID. The processor completes the first operation by using the second ID and/or the third ID to identify the first task to at least a first data structure. In one implementation, the first operation is a memory access operation and the first data structure is a set of page tables. Also, in one implementation, the second ID identifies a first application of the first task and the third ID identifies a first operating system (OS) of the first task.

公开(公告)号：US20200034151A1

公开(公告)日：2020-01-30

申请号：US16043293

申请日：2018-07-24

Applicant: ADVANCED MICRO DEVICES, INC.

Inventor： Aparna THYAGARAJAN ,  Marius EVERS ,  Arunachalam ANNAMALAI

IPC: G06F9/38 ,  G06F9/30

Abstract: A processor includes a branch target buffer (BTB) having a plurality of entries whereby each entry corresponds to an associated instruction pointer value that is predicted to be a branch instruction. Each BTB entry stores a predicted branch target address for the branch instruction, and further stores information indicating whether the next branch in the block of instructions associated with the predicted branch target address is predicted to be a return instruction. In response to the BTB indicating that the next branch is predicted to be a return instruction, the processor initiates an access to a return stack that stores the return address for the predicted return instruction. By initiating access to the return stack responsive to the return prediction stored at the BTB, the processor reduces the delay in identifying the return address, thereby improving processing efficiency.

公开(公告)号：US10546365B2

公开(公告)日：2020-01-28

申请号：US15843968

申请日：2017-12-15

Applicant: ADVANCED MICRO DEVICES, INC. ,  ATI TECHNOLOGIES ULC

Inventor： Michael Mantor ,  Laurent Lefebvre ,  Mika Tuomi ,  Kiia Kallio

IPC: G06T3/40 ,  G06T1/20 ,  G06T3/00 ,  G06T15/80 ,  G06T15/00

Abstract: An apparatus, such as a head mounted device (HMD), includes one or more processors configured to implement a graphics pipeline that renders pixels in window space with a nonuniform pixel spacing. The apparatus also includes a first distortion function that maps the non-uniformly spaced pixels in window space to uniformly spaced pixels in raster space. The apparatus further includes a scan converter configured to sample the pixels in window space through the first distortion function. The scan converter is configured to render display pixels used to generate an image for display to a user based on the uniformly spaced pixels in raster space. In some cases, the pixels in the window space are rendered such that a pixel density per subtended area is constant across the user's field of view.

公开(公告)号：US10540802B1

公开(公告)日：2020-01-21

申请号：US16263986

申请日：2019-01-31

Applicant: ADVANCED MICRO DEVICES, INC.

Inventor： Maxim V. Kazakov ,  Mark Fowler

IPC: G06T15/04 ,  G06T15/00

Abstract: A processor receives a request to access one or more levels of a partially resident texture (PRT) resource. The levels represent a texture at different levels of detail (LOD) and the request includes normalized coordinates indicating a location in the texture. The processor accesses a texture descriptor that includes dimensions of a first level of the levels and one or more offsets between a reference level and one or more second levels that are associated with one or more residency maps that indicate texels that are resident in the PRT resource. The processor translates the normalized coordinates to texel coordinates in the one or more residency maps based on the offset and accesses, in response to the request, the one or more residency maps based on the texel coordinates to determine whether texture data indicated by the normalized coordinates is resident in the PRT resource.

公开(公告)号：US10540200B2

公开(公告)日：2020-01-21

申请号：US15809940

申请日：2017-11-10

Applicant: Advanced Micro Devices, Inc.

Inventor： Kevin Y. Cheng ,  David A. Roberts ,  William C. Brantley

IPC: G06F9/46 ,  G06F9/50 ,  G06F13/40 ,  G06F13/42

Abstract: A hardware context manager in a field-programmable gate array (FPGA) device includes configuration logic configured to program one or more programming regions in the FPGA device based on configuration data for implementing a target configuration of the one or more programming regions. Context management logic in the hardware context manager is coupled with the configuration logic and saves a first context corresponding to the target configuration by retrieving first state information from the set of one or more programming regions, where the first state information is generated based on the target configuration, and storing the retrieved first state information in a context memory. The context management logic restores the first context by transferring the first state information from the context memory to the one or more programming regions, and causing the configuration logic to program the one or more programming regions based on the configuration data.