公开(公告)号：US12040226B2

公开(公告)日：2024-07-16

申请号：US18137334

申请日：2023-04-20

Applicant: Intel Corporation

Inventor： Sean King ,  Hui Jae Yoo ,  Sreenivas Kosaraju ,  Timothy Glassman

IPC: H01L21/76 ,  H01L21/02 ,  H01L21/768 ,  H01L23/00 ,  H01L23/52 ,  H01L23/522 ,  H01L23/532

CPC classification number: H01L21/76831 ,  H01L21/02178 ,  H01L21/022 ,  H01L21/0228 ,  H01L21/76802 ,  H01L21/7682 ,  H01L21/76829 ,  H01L21/76877 ,  H01L23/522 ,  H01L23/5222 ,  H01L23/5226 ,  H01L23/53228 ,  H01L23/53295 ,  H01L23/564 ,  H01L2924/0002 ,  H01L2924/0002 ,  H01L2924/00

Abstract: Conformal hermetic dielectric films suitable as dielectric diffusion barriers over 3D topography. In embodiments, the dielectric diffusion barrier includes a dielectric layer, such as a metal oxide, which can be deposited by atomic layer deposition (ALD) techniques with a conformality and density greater than can be achieved in a conventional silicon dioxide-based film deposited by a PECVD process for a thinner contiguous hermetic diffusion barrier. In further embodiments, the diffusion barrier is a multi-layered film including a high-k dielectric layer and a low-k or intermediate-k dielectric layer (e.g., a bi-layer) to reduce the dielectric constant of the diffusion barrier. In other embodiments a silicate of a high-k dielectric layer (e.g., a metal silicate) is formed to lower the k-value of the diffusion barrier by adjusting the silicon content of the silicate while maintaining high film conformality and density.

公开(公告)号：US12039421B2

公开(公告)日：2024-07-16

申请号：US17122384

申请日：2020-12-15

Applicant: Intel Corporation

Inventor： Yingyu Miao ,  Ning Xue

IPC: G06F17/16 ,  G06N20/00 ,  H03M7/30 ,  G06F11/14

CPC classification number: G06N20/00 ,  G06F17/16 ,  H03M7/3088 ,  H03M7/702 ,  G06F11/14

Abstract: An apparatus to facilitate deep learning numeric data and sparse matrix compression is disclosed. The apparatus includes a processor comprising a compression engine to: receive a data packet comprising a plurality of cycles of data samples, and for each cycle of the data samples: pass the data samples of the cycle to a compressor dictionary; identify, from the compressor dictionary, tags for each of the data samples, wherein the compressor dictionary comprises at least a first tag for data having a value of zero and a second tag for data having a value of one; and compress the data samples into compressed cycle data by storing the tags as compressed data, wherein the data samples identified with the first tag are compressed using the first tag and the data samples identified with the second tag are compressed using the second tag at the same time as values of the data samples identified with the first tag or the second tag are excluded from the compressed cycle data.

公开(公告)号：US12039234B2

公开(公告)日：2024-07-16

申请号：US17723217

申请日：2022-04-18

Applicant: Intel Corporation

Inventor： Anne Matsuura ,  Sonika Johri ,  Justin Hogaboam

IPC: G06F30/20 ,  G06N10/00

CPC classification number: G06F30/20 ,  G06N10/00

Abstract: Apparatus and method for a full quantum system simulator. For example, one embodiment of a method comprises: initializing a quantum computing system simulator for simulating multiple layers of a quantum system including one or more non-quantum layers and one or more physical quantum device layers of the quantum system; simulating a first set of operations of the one or more non-quantum layers of the quantum system to generate first simulation results; simulating a second set of operations of the one or more quantum device layers of the quantum system to generate second simulation results; analyzing the first and second simulation results to provide at least one configuration recommendation for the quantum system.

公开(公告)号：US12038861B2

公开(公告)日：2024-07-16

申请号：US17973268

申请日：2022-10-25

Applicant: Intel Corporation

Inventor： Francesc Guim Bernat ,  Da-Ming Chiang ,  Kshitij A. Doshi ,  Suraj Prabhakaran ,  Mark A. Schmisseur

IPC: G06F13/40 ,  G06F9/455 ,  G06F9/50 ,  G06F9/54 ,  G06F13/362 ,  G06F13/42 ,  G06N3/02 ,  G06N3/04 ,  G06N3/045 ,  G06N3/08

CPC classification number: G06F13/4068 ,  G06F9/45533 ,  G06F9/5027 ,  G06F9/54 ,  G06F13/362 ,  G06F13/4265 ,  G06F13/4282 ,  G06N3/02 ,  G06N3/04 ,  G06N3/045 ,  G06N3/08 ,  G06F2213/0026

Abstract: There is disclosed an example of an artificial intelligence (AI) system, including: a first hardware platform; a fabric interface configured to communicatively couple the first hardware platform to a second hardware platform; a processor hosted on the first hardware platform and programmed to operate on an AI problem; and a first training accelerator, including: an accelerator hardware; a platform inter-chip link (ICL) configured to communicatively couple the first training accelerator to a second training accelerator on the first hardware platform without aid of the processor; a fabric ICL to communicatively couple the first training accelerator to a third training accelerator on a second hardware platform without aid of the processor; and a system decoder configured to operate the fabric ICL and platform ICL to share data of the accelerator hardware between the first training accelerator and second and third training accelerators without aid of the processor.

公开(公告)号：US12037434B2

公开(公告)日：2024-07-16

申请号：US17313932

申请日：2021-05-06

Applicant: Intel Corporation

Inventor： Eungnak Han ,  Gurpreet Singh ,  Tayseer Mahdi ,  Florian Gstrein ,  Lauren Doyle ,  Marie Krysak ,  James Blackwell ,  Robert Bristol

IPC: C08F265/04 ,  C08F265/02 ,  G03F7/11 ,  H01L23/522 ,  H01L23/528

CPC classification number: C08F265/04 ,  C08F265/02 ,  G03F7/11 ,  H01L23/5226 ,  H01L23/528

Abstract: A chemical composition includes a polymer chain having a surface anchoring group at a terminus of the polymer chain. The surface anchoring group is metal or dielectric selective and the polymer chain further includes at least one of a photo-acid generator, quencher, or a catalyst. In some embodiments, the surface anchoring group is metal selective or dielectric selective. In some embodiments, the polymer chain includes side polymer chains where the side polymer chains include polymers of photo-acid generators, quencher, or catalyst.

公开(公告)号：US20240237082A1

公开(公告)日：2024-07-11

申请号：US18559004

申请日：2022-09-16

Applicant: Intel Corporation

Inventor： Seau Sian LIM ,  Marta MARTINEZ TARRADELL ,  Yi GUO ,  Sudeep PALAT ,  Candy YIU ,  Yujian ZHANG ,  Ansab ALI ,  Youn Hyoung HEO

IPC: H04W74/0833 ,  H04W74/00

CPC classification number: H04W74/0833 ,  H04W74/002

Abstract: Various embodiments herein are directed to using random access channel (RACH) configuration parameters to identify multiple features and combinations of features. In particular, some embodiments are directed to extensions to RACH configuration information elements (IEs) to identify multiple features and feature combinations.

公开(公告)号：US20240236787A1

公开(公告)日：2024-07-11

申请号：US18557269

申请日：2022-10-20

Applicant: Intel Corporation

Inventor： Meng ZHANG ,  Andrey CHERVYAKOV ,  Rui HUANG ,  Hua LI ,  Ilya BOLOTIN

IPC: H04W36/00 ,  H04W76/28

CPC classification number: H04W36/0088 ,  H04W76/28

Abstract: The invention relates to an apparatus comprising: memory to store measurement gap configuration information associated with network switching for a user equipment (UE); and processing circuitry to: retrieve the measurement gap configuration information from the memory, wherein the measurement gap configuration information includes a measurement gap pattern having: a measurement gap length (MGL) of 20 ms, 40 ms, 80 ms, or 160 ms, and a measurement gap repetition period of 5120 ms; and encode a message for transmission to the UE that includes the measurement gap configuration information.

公开(公告)号：US20240236541A9

公开(公告)日：2024-07-11

申请号：US17971931

申请日：2022-10-24

Applicant: Intel Corporation

Inventor： Oren Haggai ,  Gila Kamhi ,  Shmuel Markovich Golan ,  Shuki Perlman ,  Prasanna Desai

IPC: H04R1/10 ,  G06F3/16 ,  H04R1/08

CPC classification number: H04R1/1041 ,  G06F3/165 ,  H04R1/08 ,  H04R1/1016 ,  H04R1/1083 ,  H04R2420/07

Abstract: An apparatus can include at least one audio device configured to detect sound. The apparatus can further include processing circuitry to determine presence of a relevant sound relevant to a user of the apparatus based on a user preference or an audio device parameter. The processing circuitry can further, responsive to detecting presence of the relevant sound, provide a control command to a user listening device to command the user listening device to provide the relevant sound to a microphone of the user listening device.

公开(公告)号：US20240235772A1

公开(公告)日：2024-07-11

申请号：US18558347

申请日：2022-08-04

Applicant: Intel Corporation

Inventor： Guotong WANG ,  Alexei DAVYDOV

IPC: H04L5/00

CPC classification number: H04L5/0051 ,  H04L5/001

Abstract: Systems, apparatus, methods, and computer-readable media provided for collision handling for sounding reference signal (SRS) transmission include one or more processors to receive configuration information for a first sounding reference signal (SRS) resource set and a second SRS resource set, wherein there is a guard period between SRS occasions of the first SRS resource set and respective SRS occasions of the second SRS resource set, determine that a first SRS occasion of the first SRS resource set and a second SRS occasion of the second SRS resource set are dropped based on a collision handling rule and encode an uplink message for transmission in the guard period between the first and second SRS occasions based on the determination.

公开(公告)号：US20240235733A1

公开(公告)日：2024-07-11

申请号：US18613935

申请日：2024-03-22

Applicant: INTEL CORPORATION

Inventor： NAUSHEEN ANSARI ,  ZIV KABIRY ,  GAL YEDIDIA

IPC: H04L1/00 ,  H03M5/14 ,  H03M13/15 ,  H03M13/29 ,  H03M13/31

CPC classification number: H04L1/0057 ,  H03M5/145 ,  H03M13/1515 ,  H03M13/2906 ,  H03M13/31 ,  H04L1/0041

Abstract: Disclosed herein are techniques to provide forward error correction for a high-speed interconnect symbol stream, such as, DisplayPort. The symbol stream may be split into FEC blocks and parity bits generated for each of the FEC blocks. The parity bits may be interleaved, encoded, and transmitted over an interconnect along with the symbol stream to provide forward error correction for the symbol stream.