公开(公告)号：US20040268355A1

公开(公告)日：2004-12-30

申请号：US10831539

申请日：2004-04-23

Applicant: STMICROELECTRONICS SA

Inventor： Frederic Robin ,  Alain Artieri ,  Stephane Audrain ,  Jacques Dumarest ,  Vincent Lefftz

IPC: G06F009/46

CPC classification number: G06F9/52 ,  H04N19/42

Abstract: Systems and methods are provided for processing different concurrent tasks by a subsystem managed by a central processor. Each tasks is comprised of successive messages including a first message, intermediate messages, and a last message. Each intermediate message comprises a subtask parameter and a link to the next message that indicates the time when the next message is to be processed. The central processor and the subsystem are connected to a storage memory and several counters associated with respective tasks. The system and method reduce task disruptions of the system.

Abstract translation: 提供了系统和方法，用于通过由中央处理器管理的子系统来处理不同的并发任务。 每个任务由包括第一消息，中间消息和最后消息的连续消息组成。 每个中间消息包括子任务参数和指向下一个消息的链接，指示下一个消息要被处理的时间。 中央处理器和子系统连接到存储存储器和与相应任务相关联的若干计数器。 系统和方法减少系统的任务中断。

公开(公告)号：US20040264556A1

公开(公告)日：2004-12-30

申请号：US10849543

申请日：2004-05-19

Applicant: STMicroelectronics SA

Inventor： Benoit Moussu ,  Steven Fluxman

IPC: H04B001/707

CPC classification number: H04B1/7117 ,  H04B2201/70707

Abstract: A receiver includes an input for receiving an input signal comprising a plurality of symbols from a plurality of multi-path transmission channels, and a plurality of fingers are connected to the input. Each finger includes a plurality of demodulation units assigned to the plurality of multi-path transmission channels for demodulation thereof, and each demodulation unit includes a channel correction circuit. A shared memory is upstream from the channel correction circuits and is shared by the demodulation units for performing a delay function therefore. A controller successively time-division multiplexes read and write access operations to the shared memory during successive time slots so that one symbol, for each active multi-path transmission channel, can be read and written during each time slot.

Abstract translation: 接收机包括用于从多个多路传输信道接收包括多个符号的输入信号的输入端，并且多个指状物连接到输入端。 每个手指包括分配给多个多径传输信道的多个解调单元以进行解调，并且每个解调单元包括信道校正电路。 共享存储器是从信道校正电路的上游，并由解调单元共享用于执行延迟功能。 控制器在连续的时隙期间对共享存储器进行连续时分复用读取和写入访问操作，从而可以在每个时隙期间读取和写入每个活动多路径传输通道的一个符号。

公开(公告)号：US20040228408A1

公开(公告)日：2004-11-18

申请号：US10742602

申请日：2003-12-19

Applicant: STMICROELECTRONICS SA

Inventor： Frederic Roelens

IPC: H04N007/12

CPC classification number: H04N5/783 ,  H04N5/781 ,  H04N5/85 ,  H04N9/8042

Abstract: A process for the decoding and displaying in forward mode at a theoretical speed xN of pictures coded according to the MPEG standard applies decoding and display rules, according to the value of a delay of the pictures displayed with respect to theoretical pictures specified by display at theoretical speed, according to specified thresholds (N1, N2, N3, N4).

Abstract translation: 根据MPEG标准编码的图像的理论速度xN，以正向模式进行解码和显示的处理根据关于由理论上显示指定的理论图像显示的图像的延迟的值来应用解码和显示规则 速度，根据指定的阈值（N1，N2，N3，N4）。

公开(公告)号：US20040226999A1

公开(公告)日：2004-11-18

申请号：US10873915

申请日：2004-06-22

Applicant: STMicroelectronics SA

Inventor： Ludovic Ruat ,  Olivier Ferrand ,  Bruno Gailhard

IPC: G06K007/06

CPC classification number: G06K7/0069 ,  G06K7/0013 ,  G06K7/006 ,  G06K7/0086 ,  Y10T307/937

Abstract: A smart card reader includes a housing for receiving a smart card, a microprocessor, and a connector for connecting the microprocessor to the received smart card for establishing communications therebetween. A voltage source provides a power supply voltage to the microprocessor based upon the smart card being received in the housing. The smart card reader further includes a first switch interposed between the voltage source and a power supply terminal of the microprocessor. The first switch is closed when the received smart card is at an end of travel in the housing so that the power supply voltage is provided to the microprocessor, and is opened when the received smart card is no longer at the end of travel in the housing so that the power supply voltage is not provided to the microprocessor.

公开(公告)号：US20040225704A1

公开(公告)日：2004-11-11

申请号：US10768997

申请日：2004-01-30

Applicant: STMicroelectronics SA

Inventor： Joel Cambonie

IPC: G06F007/38

CPC classification number: G06F7/5324 ,  G06F7/57 ,  G06F15/7867 ,  G06F2207/382 ,  H03K19/17728 ,  H03K19/17732 ,  H03K19/17736

Abstract: A configurable electronic circuit includes at least one tile that includes a plurality of cells interconnected. Each cell includes a multiplier, an arithmetic and logic unit for performing at least one arithmetic and/or logic function from a set of functions, a vertical bus, and a first configurable switching circuit connected to the vertical bus and to inputs of the multiplier. Each cell further includes a second configurable switching circuit connected to the vertical bus and to an output of the multiplier, a third configurable switching circuit connected to the vertical bus and to an output of the multiplier in a different cell, a fourth configurable switching circuit connected to the vertical bus and to inputs of the arithmetic and logic unit, and a fifth configurable switching circuit connected to the vertical bus and to an output of the arithmetic and logic unit.

Abstract translation: 可配置电子电路包括至少一个瓦片，其包括互连的多个单元。 每个单元包括乘法器，算术和逻辑单元，用于从一组函数执行至少一个算术和/或逻辑函数，垂直总线以及连接到垂直总线和乘法器的输入的第一可配置开关电路。 每个单元还包括连接到垂直总线和乘法器的输出的第二可配置开关电路，连接到垂直总线和不同单元中乘法器的输出的第三可配置开关电路，连接到第四可配置开关电路 到垂直总线和算术和逻辑单元的输入，以及连接到垂直总线和算术和逻辑单元的输出的第五可配置开关电路。

公开(公告)号：US20040190867A1

公开(公告)日：2004-09-30

申请号：US10741821

申请日：2003-12-19

Applicant: STMICROELECTRONICS SA

Inventor： Frederic Roelens

IPC: H04N005/783

CPC classification number: H04N5/783 ,  H04N5/781 ,  H04N5/85 ,  H04N9/8042

Abstract: A process for decoding and for displaying in rewind mode pictures of a stream of picture data compressed according to the MPEG standard using a specified number N of frame memories each adapted for storing a decoded picture, where N is an integer greater than or equal to 4, applies rules for selecting a frame memory when a frame memory is to be overwritten so as to allow the storage of a new picture to be decoded.

Abstract translation: 一种用于解码和用于在倒带模式中显示根据MPEG标准压缩的图像数据流的图像的处理，其使用指定数量的N个适用于存储解码图像的帧存储器，其中N是大于或等于4的整数 当帧存储器被重写时，应用用于选择帧存储器的规则，以允许新图像的存储被解码。

公开(公告)号：US20040185598A1

公开(公告)日：2004-09-23

申请号：US10739871

申请日：2003-12-18

Applicant: STMICROELECTRONICS SA

Inventor： Baudoin Lecohier ,  Brendan Dunne

IPC: H01L021/00

CPC classification number: H01L27/146 ,  H01L31/02162 ,  H01L31/02327 ,  H01L31/18

Abstract: The invention relates to a to a process for making a semiconductor color image sensor cell comprising a metal layer in which a fixed contact is defined, an anti-reflecting layer covering the metal layer and a passivation layer covering the assembly. The method includes etching the passivation layer and stopping on the anti-reflecting layer so as to form a hole for the opening of the fixed contact; forming at least one colored filter element on a region of the passivation layer, the anti-reflecting layer then acting as a protection layer for the surface of the fixed contact; depositing a planarizing resin layer so as to cover the colored filter elements; forming micro-lenses on the planarizing resin layer above the colored filter elements; and etching the anti-reflecting layer to open the fixed contact.

Abstract translation: 本发明涉及一种制造半导体彩色图像传感器单元的方法，该单元包括限定有固定触点的金属层，覆盖金属层的抗反射层和覆盖该组件的钝化层。 该方法包括蚀刻钝化层并停止在抗反射层上，以便形成用于打开固定触点的孔; 在钝化层的区域上形成至少一个有色过滤元件，然后防反射层充当固定触点表面的保护层; 沉积平坦化树脂层以覆盖着色滤色器元件; 在着色过滤元件上方的平坦化树脂层上形成微透镜; 并且蚀刻抗反射层以打开固定触点。

公开(公告)号：US20040152435A1

公开(公告)日：2004-08-05

申请号：US10718493

申请日：2003-11-20

Applicant: STMicroelectronics SA

Inventor： Bruno Pellat ,  Sylvie Gellida

IPC: H04B001/26

CPC classification number: H03D7/145 ,  H03D7/1458 ,  H03D7/1491 ,  H03D7/165

Abstract: A frequency transposition device includes a current switching circuit with two differential pairs of transistors being controlled by a local oscillator signal. In a current switching circuit calibration mode, the local oscillator is rendered inactive and the two pairs of transistors are calibrated in succession by zeroing the ground path current of one of the pairs of transistors not undergoing calibration, and by setting the voltage difference applied to the bases of the transistors of the pair of transistors undergoing calibration. This is done until the output voltage of the frequency transposition device is zeroed to within a predetermined accuracy. The base voltage difference obtained is stored after calibration. In a normal operating mode the local oscillator is rendered active, and the two stored voltage differences are applied to the respective bases of the two differential pairs of transistors.

Abstract translation: 频率转置装置包括具有由本地振荡器信号控制的两个差分对晶体管的电流切换电路。 在当前的开关电路校准模式中，本地振荡器变为无效，并且两对晶体管被连续校准，通过使未进行校准的晶体管对之一的接地路径电流归零，并且通过将施加到 一对晶体管的晶体管的基极进行校准。 直到频率转置装置的输出电压被调零到预定精度为止。 获得的基准电压差在校准后存储。 在正常操作模式中，本地振荡器被激活，并且两个存储的电压差被施加到两个差分对晶体管的相应基极。

公开(公告)号：US20040146111A1

公开(公告)日：2004-07-29

申请号：US10702220

申请日：2003-11-05

Applicant: STMICROELECTRONICS SA

Inventor： Denis Dutey ,  Nikola Cornij

IPC: H04N007/12

CPC classification number: H04N21/2662 ,  H04N5/4401 ,  H04N5/45 ,  H04N5/85 ,  H04N7/012 ,  H04N9/8042 ,  H04N9/8227 ,  H04N19/112 ,  H04N19/12 ,  H04N19/156 ,  H04N19/172 ,  H04N19/40 ,  H04N19/46 ,  H04N21/25808 ,  H04N21/4312 ,  H04N21/4348 ,  H04N21/4355 ,  H04N21/4884

Abstract: A method of transcoding a sub-picture unit each comprising encoded sub-picture pixel data including sub-picture lines separated into at least a first field and a second field as well as a set of display control commands associated with the sub-picture pixel data, comprises the step of pre-processing (53) the display control commands to prepare transcoding to frame format. Encoded lines of said top and bottom fields are then merged (56,73) into a single encoded frame and the display control commands are modified (56,74) according to changes in encoded sub-picture pixel data before outputting.

Abstract translation: 一种副图像单元的代码转换方法，每个子图像单元包括被编码的子图像像素数据，该子图像像素数据包括分成至少第一场和第二场的子图像线以及与子图像像素数据相关联的一组显示控制命令 包括对显示控制命令进行预处理（53）以准备对帧格式的转码的步骤。 然后，所述顶部和底部场的编码行被合并（56,73）到单个编码帧中，并且根据编码的子图像像素数据在输出之前的变化来修改显示控制命令（56,74）。

公开(公告)号：US20040135234A1

公开(公告)日：2004-07-15

申请号：US10701165

申请日：2003-11-04

Applicant: STMicroelectronics SA

Inventor： Pierre Morin ,  Jorge Luis Regolini

IPC: H01L023/58

CPC classification number: H01L29/7842 ,  H01L21/823814 ,  H01L21/823828 ,  H01L23/3171 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A semiconductor device includes a substrate, MOS transistors in the substrate, and a dielectric layer on the MOS transistors. Contact holes are formed through the dielectric layer to provide electrical connection to the MOS transistors. An etch-stop layer is between the MOS transistors and the dielectric layer. The etch-stop layer includes a first layer of material having a first residual stress level and covers some of the MOS transistors, and a second layer of material having a second residual stress level and covers all of the MOS transistors. The respective thickness of the first and second layers of material, and the first and second residual stress levels associated therewith are selected to obtain variations in operating parameters of the MOS transistors.

Abstract translation: 半导体器件包括衬底，衬底中的MOS晶体管和MOS晶体管上的介电层。 通过介电层形成接触孔以提供与MOS晶体管的电连接。 蚀刻停止层位于MOS晶体管和电介质层之间。 蚀刻停止层包括具有第一残余应力水平并且覆盖一些MOS晶体管的第一材料层和具有第二残余应力水平并覆盖所有MOS晶体管的第二材料层。 选择第一和第二层材料的相应厚度以及与其相关联的第一和第二残余应力水平以获得MOS晶体管的操作参数的变化。