公开(公告)号：US10198014B2

公开(公告)日：2019-02-05

申请号：US15475266

申请日：2017-03-31

Applicant: STMicroelectronics International N.V.

Inventor： Kapil Kumar Tyagi ,  Nitin Gupta

IPC: G05F1/575 ,  G05F1/613

Abstract: A low dropout regulator produces output at an intermediate node. A resistive divider is coupled between the intermediate node and ground and provides a feedback signal to the low dropout regulator. A transistor has a first conduction terminal coupled to the intermediate node and a second conduction terminal coupled to an output node. A first impedance is coupled to the output node, a first switch selectively couples the first impedance to a supply node, a second impedance coupled to the output node, and a second switch selectively couples the second impedance to a ground node. Control circuitry is coupled to the control terminal of the transistor and to control terminals of the first and second switches. The control circuitry switches the electronic device to a power down mode by turning off transistor, closing the first and second switches, and turning off the low dropout regulator.

公开(公告)号：US10191118B2

公开(公告)日：2019-01-29

申请号：US15809433

申请日：2017-11-10

Applicant: STMicroelectronics International N.V.

Inventor： Daniel Ladret

IPC: G01R31/36

Abstract: The state of charge of a rechargeable battery is determined by calculating the DC impedance of the battery. The impedance is calculated by: performing a two different constant current discharges of the battery at a first and second C-rates, respectively; measuring the voltage and current during the interval of each constant current discharge and calculating the amount of charge extracted from the battery up to a point where the battery voltage drops to a threshold value; calculating the state of charge of the battery; and calculating the DC impedance of the battery as a function of the difference between the battery voltages and discharge currents for the two different discharges.

公开(公告)号：US10187650B2

公开(公告)日：2019-01-22

申请号：US14306673

申请日：2014-06-17

Applicant: STMicroelectronics International N.V.

Inventor： Sumit Johar ,  SurinderPal Singh

IPC: H04N19/433

Abstract: Video encoders and decoders and video encoding and decoding methods are provided. A video encoder includes an input buffer configured to receive a video data stream and to supply current frame data, a frame buffer configured to store reconstructed frame data, and an encoder circuit configured to read reference frame data from the frame buffer, to encode the current frame data received from the input buffer using the reference frame data and to write the reconstructed frame data to the frame buffer. The encoder circuit may be configured to write the reconstructed frame data by overwriting the reference frame data in the frame buffer.

公开(公告)号：US10134894B2

公开(公告)日：2018-11-20

申请号：US14985264

申请日：2015-12-30

Applicant: STMICROELECTRONICS INTERNATIONAL N.V.

Inventor： Anand Kumar ,  Ankit Agrawal

IPC: H01L29/78 ,  H01L21/265 ,  H01L21/311 ,  H01L21/762 ,  H01L29/06 ,  H01L29/51 ,  H01L29/66 ,  H01L27/12 ,  H01L21/84 ,  H01L29/786

Abstract: Circuit module designs that incorporate dual gate field effect transistors are implemented with fully depleted silicon-on-insulator (FD-SOI) technology. Lowering the threshold voltages of the transistors can be accomplished through dynamic secondary gate control in which a back-biasing technique is used to operate the dual gate FD-SOI transistors with enhanced switching performance. Consequently, such transistors can operate at very low core voltage supply levels, down to as low as about 0.4 V, which allows the transistors to respond quickly and to switch at higher speeds. Performance improvements are shown in circuit simulations of an inverter, an amplifier, a level shifter, and a voltage detection circuit module.

公开(公告)号：US20180330787A1

公开(公告)日：2018-11-15

申请号：US16044280

申请日：2018-07-24

Applicant: STMicroelectronics S.r.l. ,  STMicroelectronics International N.V.

Inventor： Marco Pasotti ,  Marcella Carissimi ,  Vikas Rana

IPC: G11C13/00

CPC classification number: G11C13/0069 ,  G11C13/0004 ,  G11C13/0026 ,  G11C2013/0078

Abstract: A method is provided for operating a memory device that includes an array of memory cells coupled to a plurality of bitlines. A memory cell is selected from among the array of memory cells. The selected memory cell is coupled to a selected bitline. During a program operation, a program current pulse is injected into the selected memory cell via a first switch coupled to the bitline. At an end of the program current pulse, the selected bitline is discharged via a second switch coupled to the bitline.

公开(公告)号：US10128913B2

公开(公告)日：2018-11-13

申请号：US15669380

申请日：2017-08-04

Applicant: STMicroelectronics International N.V.

Inventor： Vinko Kunc ,  Maksimiljan Stiglic ,  Kosta Kovacic ,  Albin Pevec ,  Anton Stern

IPC: H04Q5/22 ,  H04B5/00 ,  G06K19/07 ,  G06K7/10

Abstract: A circuit of an actively transmitting tag includes an antenna, a digitizer, a voltage-controlled oscillator (VCO), an output amplifier, a phase-displacement detector, and a regulator. The input of the digitizer connects to the antenna. The outputs of the digitizer and the output amplifier are connected to the input terminals of the phase-displacement detector. The output amplifier connects the output of the VCO to the antenna and the regulator connects the output of the phase-displacement detector to the VCO.

公开(公告)号：US10097799B2

公开(公告)日：2018-10-09

申请号：US15958244

申请日：2018-04-20

Applicant: STMicroelectronics International N.V.

Inventor： Mahesh Chandra ,  Brejesh Lall

IPC: H04N9/45 ,  H04N5/347 ,  H04N9/04

Abstract: An image sensor device may include an array of image sensing pixels with adjacent image sensing pixels being arranged in macropixel, and a processor coupled to the array of image sensing pixels. The processor may be configured to receive pixel signals from the array of image sensing pixels, and arrange the received pixel signals into macropixel signal sets for respective macropixels. The processor may be configured to perform, in parallel, an image enhancement operation on the received pixel signals for each macropixel signal set to generate enhanced macropixel signals, and transmit the enhanced macropixel signals.

公开(公告)号：US20180287617A1

公开(公告)日：2018-10-04

申请号：US15475274

申请日：2017-03-31

Applicant: STMicroelectronics International N.V.

Inventor： Anand Kumar ,  Nitin Gupta ,  Nitin Jain

IPC: H03L1/00 ,  H03L7/099 ,  H03L7/183

Abstract: An electronic device disclosed herein includes a locked loop circuit configured to receive a reference signal intended to have an intended frequency, wherein the locked look circuit is intended to generate an intended output signal having an intended frequency equal to the intended frequency multiplied by an intended multiplier. A frequency counter counts a number of pulses of the reference signal during a time window so as to determine an actual frequency of the reference signal. A control circuit determines an actual multiplier for the locked loop circuit that, when multiplied by the actual frequency of the reference signal, causes the locked loop circuit to generate an actual output signal having an actual frequency equal to the intended frequency.

公开(公告)号：US20180268895A1

公开(公告)日：2018-09-20

申请号：US15988140

申请日：2018-05-24

Applicant: STMicroelectronics International N.V.

Inventor： Piyush Jain ,  Vivek Asthana ,  Naveen Batra

IPC: G11C11/419 ,  G11C7/12 ,  G11C5/14

CPC classification number: G11C11/419 ,  G11C5/14 ,  G11C7/12

Abstract: A method of operating a memory device includes providing a first voltage to a memory array, providing a second voltage to a peripheral logic circuit, receiving an access request, and in response to the access request, increasing a third voltage of a bit line of the memory array during a precharge phase.

公开(公告)号：US10050524B1

公开(公告)日：2018-08-14

申请号：US15800896

申请日：2017-11-01

Applicant: STMicroelectronics International N.V.

Inventor： Vikas Rana

IPC: H02M3/18 ,  H02M3/07 ,  H01L27/092 ,  H01L27/06 ,  H01L27/02

Abstract: A voltage multiplier circuit operates in response to a received clock signal to perform a voltage multiplication operation on an input voltage to generate an output voltage. The voltage multiplier circuit includes a pair of intermediate nodes that are capacitively coupled to receive, respectively, opposite phases of a clock signal. A first CMOS driver circuit is coupled to one of the intermediate nodes and has an output configured to generate one phase of a level shifted output clock signal. A second CMOS driver circuit is coupled to another one of the intermediate nodes and has an output configured to generate another phase of the level shifted output clock signal.