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    Dual gate FD-SOI transistor
    2.
    发明授权
    Dual gate FD-SOI transistor 有权

    公开(公告)号：US10134894B2

    公开(公告)日：2018-11-20

    申请号：US14985264

    申请日：2015-12-30

    Applicant: STMICROELECTRONICS INTERNATIONAL N.V.

    Inventor： Anand Kumar ,  Ankit Agrawal

    IPC: H01L29/78 ,  H01L21/265 ,  H01L21/311 ,  H01L21/762 ,  H01L29/06 ,  H01L29/51 ,  H01L29/66 ,  H01L27/12 ,  H01L21/84 ,  H01L29/786

    Abstract: Circuit module designs that incorporate dual gate field effect transistors are implemented with fully depleted silicon-on-insulator (FD-SOI) technology. Lowering the threshold voltages of the transistors can be accomplished through dynamic secondary gate control in which a back-biasing technique is used to operate the dual gate FD-SOI transistors with enhanced switching performance. Consequently, such transistors can operate at very low core voltage supply levels, down to as low as about 0.4 V, which allows the transistors to respond quickly and to switch at higher speeds. Performance improvements are shown in circuit simulations of an inverter, an amplifier, a level shifter, and a voltage detection circuit module.

    DUAL GATE FD-SOI TRANSISTOR
    3.
    发明申请
    DUAL GATE FD-SOI TRANSISTOR 审中-公开
    双门FD-SOI晶体管

    公开(公告)号：US20150129967A1

    公开(公告)日：2015-05-14

    申请号：US14231459

    申请日：2014-03-31

    Applicant: STMicroelectronics International N.V.

    Inventor： Anand Kumar ,  Ankit Agrawal

    IPC: H01L27/12 ,  H01L29/78 ,  H01L21/265 ,  H01L21/8238 ,  H01L21/762 ,  H01L21/266 ,  H01L27/092 ,  H01L21/84

    CPC classification number: H01L29/7831 ,  H01L21/26513 ,  H01L21/31111 ,  H01L21/7624 ,  H01L21/84 ,  H01L27/1203 ,  H01L29/0649 ,  H01L29/51 ,  H01L29/517 ,  H01L29/66484 ,  H01L29/78648

    Abstract: Circuit module designs that incorporate dual gate field effect transistors are implemented with fully depleted silicon-on-insulator (FD-SOI) technology. Lowering the threshold voltages of the transistors can be accomplished through dynamic secondary gate control in which a back-biasing technique is used to operate the dual gate FD-SOI transistors with enhanced switching performance. Consequently, such transistors can operate at very low core voltage supply levels, down to as low as about 0.4 V, which allows the transistors to respond quickly and to switch at higher speeds. Performance improvements are shown in circuit simulations of an inverter, an amplifier, a level shifter, and a voltage detection circuit module.

    Abstract translation: 具有双栅极场效应晶体管的电路模块设计采用完全耗尽的绝缘体上硅（FD-SOI）技术实现。 降低晶体管的阈值电压可以通过动态辅助栅极控制来实现，其中使用反向偏置技术来操作具有增强的开关性能的双栅极FD-SOI晶体管。 因此，这样的晶体管可以以低至约0.4V的非常低的核心电压供应电平工作，这允许晶体管快速响应并以更高的速度切换。 在逆变器，放大器，电平转换器和电压检测电路模块的电路仿真中示出了性能改进。

    NOVEL METHODOLOGY TO AVOID GATE STRESS FOR LOW VOLTAGE DEVICES IN FDSOI TECHNOLOGY
    4.
    发明申请
    NOVEL METHODOLOGY TO AVOID GATE STRESS FOR LOW VOLTAGE DEVICES IN FDSOI TECHNOLOGY 审中-公开
    用于避免FDSOI技术中低电压设备的栅极应力的新方法

    公开(公告)号：US20160301404A1

    公开(公告)日：2016-10-13

    申请号：US15185514

    申请日：2016-06-17

    Applicant: STMicroelectronics International N.V.

    Inventor： Ankit Agrawal

    IPC: H03K17/10 ,  H01L27/12 ,  H03K17/687 ,  H01L29/06 ,  H01L29/10 ,  H01L27/092 ,  H01L29/78

    CPC classification number: H03K17/102 ,  H01L27/092 ,  H01L27/1203 ,  H01L29/0653 ,  H01L29/1033 ,  H01L29/42364 ,  H01L29/7838 ,  H01L29/78648 ,  H03K17/6872

    Abstract: A CMOS device is formed in an FDSOI integrated circuit die. By retrieving the MOS functionality for gate voltage levels higher than its stress limits, second gate availability in these devices is being used, and hence removing the additional circuitry that would have been used for protecting the devices from such stress. Implementation in an inverter includes a PMOS transistor and an NMOS transistor. The PMOS and NMOS transistors each include a first gate coupled to the respective source terminal of the transistor. The PMOS and NMOS transistors each include a back gate coupled to the input of the inverter.

    Abstract translation: 在FDSOI集成电路管芯中形成CMOS器件。 通过检测高于其应力限制的栅极电压电平的MOS功能，正在使用这些器件中的第二栅极可用性，因此去除了已经用于保护器件免受这种应力的附加电路。 反相器中的实现包括PMOS晶体管和NMOS晶体管。 PMOS和NMOS晶体管各自包括耦合到晶体管的相应源极端子的第一栅极。 PMOS和NMOS晶体管各自包括耦合到反相器的输入的背栅。

    Wide range core supply compatible level shifter circuit
    6.
    发明授权
    Wide range core supply compatible level shifter circuit 有权
    宽范围内核电源兼容电平转换电路

    公开(公告)号：US09178517B2

    公开(公告)日：2015-11-03

    申请号：US14078236

    申请日：2013-11-12

    Applicant: STMicroelectronics International N.V.

    Inventor： Ankit Agrawal

    IPC: H03L5/00 ,  H03K19/0185 ,  H03K19/00 ,  H03K19/017

    CPC classification number: H03K19/0185 ,  H03K3/356113 ,  H03K19/0013 ,  H03K19/017

    Abstract: A level shifter circuit is implemented with dual gate fully depleted silicon-on-insulator (FDSOI) technology. By enhancing the performance of the NMOS and devices within the level shifting circuit, the Vt of the dual gate FDSOI NMOS transistors is lowered without a need for additional control circuitry. Lowering the Vt can be accomplished through dynamic secondary gate control, by coupling together primary and secondary gates of the NMOS devices, while secondary gates of the PMOS devices can be coupled to a high voltage supply level. Such high performance NMOS devices can then operate at higher frequencies and run on a much wider range of core power supplies. Meanwhile, conventional DC conditions are maintained during steady state operation. Because no components are added to the level shifter circuit, the higher performance is achieved without an increase in size and current consumption.

    Abstract translation: 电平移位器电路采用双栅绝缘体绝缘体（FDSOI）技术实现。 通过提高电平移位电路中的NMOS和器件的性能，双栅极FDSOI NMOS晶体管的Vt降低，而不需要额外的控制电路。 降低Vt可以通过将NMOS器件的初级栅极和次级栅极耦合在一起的动态二次栅极控制来实现，而PMOS器件的次级栅极可以耦合到高电压电平。 这样的高性能NMOS器件然后可以在更高的频率下运行并在更宽的核心电源范围上运行。 同时，在稳态操作期间保持传统的直流条件。 因为没有组件被添加到电平移位器电路，所以在不增加尺寸和电流消耗的情况下实现更高的性能。

    Low current, wide range input common mode LVDS receiver devices and methods
    7.
    发明授权
    Low current, wide range input common mode LVDS receiver devices and methods 有权

    公开(公告)号：US11223354B2

    公开(公告)日：2022-01-11

    申请号：US16999813

    申请日：2020-08-21

    Applicant: STMicroelectronics International N.V.

    Inventor： Paras Garg ,  Ankit Agrawal ,  Sandeep Kaushik

    IPC: H03K19/0185 ,  H03K17/687 ,  H03K5/24

    Abstract: Low-voltage differential signaling (LVDS) receiver circuits, electronic devices, and methods are provided. A LVDS receiver includes an input differential pair of transistors that receive a differential input signal. The input differential pair includes a first NMOS transistor that receives a first input signal and a second NMOS transistor that receives a second input signal. A third NMOS transistor has source and drain terminals respectively coupled to source and drain terminals of the first NMOS transistor, and a fourth NMOS transistor has source and drain terminals respectively coupled to source and drain terminals of the second NMOS transistor. A first level shifter is coupled to a gate of the third NMOS transistor, and a second level shifter is coupled to a gate of the fourth NMOS transistor.

    WIDE RANGE CORE SUPPLY COMPATIBLE LEVEL SHIFTER CIRCUIT
    9.
    发明申请
    WIDE RANGE CORE SUPPLY COMPATIBLE LEVEL SHIFTER CIRCUIT 有权
    宽范围核心供应兼容级别更换电路

    公开(公告)号：US20150130528A1

    公开(公告)日：2015-05-14

    申请号：US14078236

    申请日：2013-11-12

    Applicant: STMicroelectronics International N.V.

    Inventor： Ankit Agrawal

    IPC: H03K19/0185 ,  H03K19/017 ,  H03K19/00

    CPC classification number: H03K19/0185 ,  H03K3/356113 ,  H03K19/0013 ,  H03K19/017

    Abstract: A level shifter circuit is implemented with dual gate fully depleted silicon-on-insulator (FDSOI) technology. By enhancing the performance of the NMOS and devices within the level shifting circuit, the Vt of the dual gate FDSOI NMOS transistors is lowered without a need for additional control circuitry. Lowering the Vt can be accomplished through dynamic secondary gate control, by coupling together primary and secondary gates of the NMOS devices, while secondary gates of the PMOS devices can be coupled to a high voltage supply level. Such high performance NMOS devices can then operate at higher frequencies and run on a much wider range of core power supplies. Meanwhile, conventional DC conditions are maintained during steady state operation. Because no components are added to the level shifter circuit, the higher performance is achieved without an increase in size and current consumption.

    Abstract translation: 电平移位器电路采用双栅绝缘体绝缘体（FDSOI）技术实现。 通过提高电平移位电路中的NMOS和器件的性能，双栅极FDSOI NMOS晶体管的Vt降低，而不需要额外的控制电路。 降低Vt可以通过将NMOS器件的初级栅极和次级栅极耦合在一起的动态二次栅极控制来实现，而PMOS器件的次级栅极可以耦合到高电压电平。 这样的高性能NMOS器件然后可以在更高的频率下运行并在更宽的核心电源范围上运行。 同时，在稳态操作期间保持传统的直流条件。 因为没有组件被添加到电平移位器电路，所以在不增加尺寸和电流消耗的情况下实现更高的性能。

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