公开(公告)号：US20190163656A1

公开(公告)日：2019-05-30

申请号：US15826065

申请日：2017-11-29

Applicant: ADVANCED MICRO DEVICES, INC. ,  ATI TECHNOLOGIES ULC

Inventor： Eric Christopher MORTON ,  Elizabeth COOPER ,  William L. WALKER ,  Douglas Benson HUNT ,  Richard Martin BORN ,  Richard H. Lee ,  Paul C. MIRANDA ,  Philip NG ,  Paul MOYER

IPC: G06F13/28 ,  G06F12/0891 ,  G06F12/0862 ,  G06F12/0815 ,  G06F12/0893

CPC classification number: G06F13/28 ,  G06F12/0815 ,  G06F12/0862 ,  G06F12/0891 ,  G06F12/0893

Abstract: A method for steering data for an I/O write operation includes, in response to receiving the I/O write operation, identifying, at an interconnect fabric, a cache of one of a plurality of compute complexes as a target cache for steering the data based on at least one of: a software-provided steering indicator, a steering configuration implemented at boot initialization, and coherency information for a cacheline associated with the data. The method further includes directing, via the interconnect fabric, the identified target cache to cache the data from the I/O write operation. The data is temporarily buffered at the interconnect fabric, and if the target cache attempts to fetch the data while the data is still buffered at the interconnect fabric, the interconnect fabric provides a copy of the buffered data in response to the fetch operation instead of initiating a memory access operation to obtain the data from memory.

公开(公告)号：US20190163471A1

公开(公告)日：2019-05-30

申请号：US15824729

申请日：2017-11-28

Applicant: Advanced Micro Devices, Inc.

Inventor： John M. King

IPC: G06F9/26 ,  G06F9/22 ,  G06F9/38 ,  G06F9/32

Abstract: A system and method for a virtual load queue is described. Load micro-operations are processed through an instruction pipeline without requiring an entry in a load queue (LDQ). An address generation scheduler queue (AGSQ) entry is allocated to the load micro-operation and a LDQ entry is not allocated to the load micro-operation. The LDQ entries are reserved for the N oldest load micro-operations, where N is the depth of the LDQ. Deallocation of the AGSQ entry is done if the load micro-operation is one of the N oldest load micro-operations, or upon successful completion of the load micro-operation. Deallocation of the AGSQ entry is not done if the load micro-operation gets a bad status and is not one of the N oldest micro-operations. Consequently, the AGSQ acts as a virtual queue for the LDQ and mitigates the limiting effect of the LDQ depth.

公开(公告)号：US10305509B2

公开(公告)日：2019-05-28

申请号：US15785127

申请日：2017-10-16

Applicant: Advanced Micro Devices, Inc.

Inventor： Greggory D. Donley ,  Vydhyanathan Kalyanasundharam ,  Bryan P. Broussard

IPC: H03M7/38 ,  H03M7/30 ,  H04B1/40 ,  G06K9/62 ,  H03M7/42 ,  H04L29/08 ,  H04L27/26 ,  H04L1/06 ,  H04L1/00 ,  H04L25/02

Abstract: Systems, apparatuses, and methods for compression of frequent data values across narrow links are disclosed. In one embodiment, a system includes a processor, a link interface unit, and a communication link. The link interface unit is configured to receive a data stream for transmission over the communication link, wherein the data stream is generated by the processor. The link interface unit determines if blocks of data of a first size from the data stream match one or more first data patterns and the link interface unit determines if blocks of data of a second size from the data stream match one or more second data patterns. The link interface unit sends, over the communication link, only blocks of data which do not match the first or second data patterns.

公开(公告)号：US10304506B1

公开(公告)日：2019-05-28

申请号：US15809608

申请日：2017-11-10

Applicant: Advanced Micro Devices, Inc. ,  ATI Technologies ULC

Inventor： Alexander J. Branover ,  Benjamin Tsien ,  Bradley Kent ,  Joyce C. Wong

IPC: H03L7/06 ,  G11C7/22 ,  G06F13/16 ,  G11C7/20

Abstract: Systems, apparatuses, and methods for implementing dynamic clock control to increase stutter efficiency in a memory subsystem are disclosed. A system includes at least a processor, a memory, and a communication fabric coupled to the processor and memory. The system implements a stutter mode for a first region of the fabric, with stutter mode including an idle state and an active state. Stutter efficiency is defined as the idle time divided by the sum of the active time and the idle time. Reducing the exit latency of going from the idle state to the active state increases the stutter efficiency which increases the power savings achieved by implementing the stutter mode. Since the phase-locked loop (PLL) is one of the main contributors to the exit latency, the PLL is powered down and one or more bypass clocks are provided during the stutter mode.

公开(公告)号：US20190158278A1

公开(公告)日：2019-05-23

申请号：US15820539

申请日：2017-11-22

Applicant: Advanced Micro Devices, Inc.

Inventor： Gongyuan Zhuang ,  Thomas R. Woller

IPC: H04L9/08 ,  H04L9/14

CPC classification number: H04L9/0822 ,  H04L9/0861 ,  H04L9/0877 ,  H04L9/0894 ,  H04L9/0897 ,  H04L9/14 ,  H04L9/302 ,  H04L9/3033

Abstract: A method and apparatus provides cryptographic keys using, for example, a cryptographic co-processor (CCP) that uses spare processor cycles to work on cryptographic key generation in advance of the keys being needed by a requestor such as an application, or other process in the device. In one example, the cryptographic co-processor detects an idle condition of the CCP such as an idle condition of a cryptographic engine in the CCP. Control logic causes the CCP to generate at least one asymmetric key component corresponding to an asymmetric cryptographic key in response to detecting the idle condition. The method and apparatus stores the asymmetric key component(s) in persistent memory and generates the asymmetric cryptographic key using the stored asymmetric key component that was generated in response to detection of the idle condition of the CCP.

公开(公告)号：US20190155979A1

公开(公告)日：2019-05-23

申请号：US15819879

申请日：2017-11-21

Applicant: Advanced Micro Devices, Inc.

Inventor： Richard T. Schultz

IPC: G06F17/50 ,  H01L27/02 ,  H01L23/528

Abstract: A system and method for laying out power grid connections for standard cells are described. In various embodiments, a standard cell includes power post and ground posts in metal zero. The metal zero posts include no vias to any upper metal layers. Some variations of the standard cell have the power and ground posts routed in metal zero to a boundary edge of the standard cell. Layout rules are changed to allow this type of routing. The power and ground posts in metal zero are connected to power and ground posts in metal zero of a neighboring cell by abutment. The place-and-route tool doesn't need to perform a further routing step after placing the cells. For other variations, the power and ground posts are not routed to the boundary edge and the place-and-route tool routes power and ground connections in metal zero between the standard cell and the neighbor cell.

公开(公告)号：US10291692B2

公开(公告)日：2019-05-14

申请号：US15298049

申请日：2016-10-19

Applicant: Advanced Micro Devices, Inc.

Inventor： Andrew G. Kegel

IPC: H04L29/06 ,  H04L29/08 ,  H04L9/32 ,  G06F21/57

Abstract: Systems, apparatuses, and methods for implementing trusted cluster attestation techniques are disclosed. A cluster includes multiple computing devices connected together and at least one cluster security module. The cluster security module collects measurement logs and attestations from N computing devices, with N being a positive integer greater than one. The cluster security module also maintains a log and calculates an attestation for its own hardware and/or software. The cluster security module combines the logs from the N computing device and the log of the cluster security module into an aggregate log, with N+1 logs combined into the aggregate log. Then, the cluster security module generates a single attestation for the cluster to represent the cluster as a whole. The cluster security module is configured to provide the single attestation and aggregate log to an external device responsive to receiving a challenge request from the external device.

公开(公告)号：US10291258B2

公开(公告)日：2019-05-14

申请号：US15605310

申请日：2017-05-25

Applicant: Advanced Micro Devices, Inc.

Inventor： Chin-Long Chen

IPC: H03M13/11 ,  H03M13/00 ,  H03M13/15 ,  H03M13/07 ,  H03M13/03 ,  H03M13/13 ,  H03M13/19

Abstract: Systems, apparatuses, and methods for generating error correction codes (ECCs) with two check symbols are disclosed. In one embodiment, a system receives a data word of length N−2 symbols, wherein N is a positive integer greater than 2, wherein each symbol has m bits, and wherein m is positive integer. The system generates a code word of length N symbols from the data word in accordance with a linear code defined by a parity check matrix. The parity check matrix is generated based on powers of γ, wherein γ is equal to β raised to the (2m/4−1) power, β is equal to a raised to the (2m/2+1) power, and α is a primitive element of GF(2m). In another embodiment, the system receives a (N, N−2) code word and decodes the code word by generating a syndrome S from the code word using the parity check matrix.

公开(公告)号：US20190141238A1

公开(公告)日：2019-05-09

申请号：US15816537

申请日：2017-11-17

Applicant: Advanced Micro Devices, Inc.

Inventor： Hui Zhou ,  Allen H. Rush ,  Yang Ling ,  Jiangli Ye

IPC: H04N5/232 ,  H04N5/265 ,  H04N5/33

Abstract: A method and apparatus of performing processing in an image capturing device includes receiving an image by the image capturing device. The image is filtered to generate a first visible light component and a second infrared component. A decontamination is performed on the infrared component to generate a decontaminated infrared component, and an interpolation is performed on the visible component to generate an interpolated visible component, both of which are provided to an image signal processor (ISP) for further processing.

公开(公告)号：US10282295B1

公开(公告)日：2019-05-07

申请号：US15825880

申请日：2017-11-29

Applicant: ADVANCED MICRO DEVICES, INC.

Inventor： William L. Walker ,  Michael W. Boyer ,  Yasuko Eckert ,  Gabriel H. Loh

IPC: G06F12/08 ,  G06F12/0817 ,  G06F12/0831 ,  G06F12/0811 ,  G06F12/128

Abstract: A method includes monitoring, at a cache coherence directory, states of cachelines stored in a cache hierarchy of a data processing system using a plurality of entries of the cache coherence directory. Each entry of the cache coherence directory is associated with a corresponding cache page of a plurality of cache pages, and each cache page representing a corresponding set of contiguous cachelines. The method further includes selectively evicting cachelines from a first cache of the cache hierarchy based on cacheline utilization densities of cache pages represented by the corresponding entries of the plurality of entries of the cache coherence directory.