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    Integrated artificial neuron device
    681.
    发明授权
    Integrated artificial neuron device 有权

    公开(公告)号：US11954589B2

    公开(公告)日：2024-04-09

    申请号：US17572899

    申请日：2022-01-11

    Applicant: STMicroelectronics SA

    Inventor： Philippe Galy ,  Thomas Bedecarrats

    IPC: G06N3/063 ,  G06N3/04 ,  G06N3/049 ,  G06N3/065 ,  G11C11/54 ,  H01L27/02 ,  H01L29/423 ,  H03K3/356

    CPC classification number: G06N3/065 ,  G06N3/049 ,  G06N3/063 ,  G11C11/54 ,  H01L27/027 ,  H01L27/0285 ,  G06N3/04 ,  H01L29/42376 ,  H03K3/356

    Abstract: An artificial-neuron device includes an integration-generation circuit coupled between an input at which an input signal is received and an output at which an output signal is delivered, and a refractory circuit inhibiting the integrator circuit after the delivery of the output signal. The refractory circuit is formed by a first MOS transistor having a first conduction-terminal coupled to a supply node, a second conduction-terminal coupled to a common node, and a control-terminal coupled to the output, and a second MOS transistor having a first conduction-terminal coupled to the input, a second conduction-terminal coupled to a reference node at which a reference voltage is received, and a control-terminal coupled to the common node. A resistive-capacitive circuit is coupled between the supply node and the reference node and having a tap coupled to the common node, with the inhibition duration being dependent upon a time constant of the resistive-capacitive circuit.

    DEVICE OF PROTECTION AGAINST ELECTROSTATIC DISCHARGES
    683.
    发明公开
    DEVICE OF PROTECTION AGAINST ELECTROSTATIC DISCHARGES 审中-公开

    公开(公告)号：US20240072036A1

    公开(公告)日：2024-02-29

    申请号：US18232032

    申请日：2023-08-09

    Applicant: STMicroelectronics SA

    Inventor： Yohann SOLARO ,  Johan BOURGEAT

    IPC: H01L27/02 ,  H01L29/74

    CPC classification number: H01L27/0248 ,  H01L29/7436

    Abstract: An electronic device includes a doped semiconductor substrate of a first conductivity type. First and second doped wells are provided, separated from each other by trench isolation, within the doped semiconductor substrate. At least one first region and at least one second region are respectively located in the first and second doped wells, with each first and second region having a doping level higher than a doping level of the first and second doped wells. The trench isolation penetrates into the first and second doped wells and extends laterally between the first region and second region. A third region laterally extends between the first and second doped wells at a location under the insulating trench. The third region has a doping level lower than the doping level of the first and second doped wells.

    PROCESSING SYSTEM, RELATED INTEGRATED CIRCUIT, DEVICE AND METHOD
    688.
    发明公开
    PROCESSING SYSTEM, RELATED INTEGRATED CIRCUIT, DEVICE AND METHOD 审中-公开

    公开(公告)号：US20230259463A1

    公开(公告)日：2023-08-17

    申请号：US18109675

    申请日：2023-02-14

    Applicant: STMicroelectronics S.r.l. ,  STMicroelectronics SA

    Inventor： Roberta VITTIMANI ,  Federico GOLLER ,  Riccardo ANGRILLI ,  Charles AUBENAS

    IPC: G06F12/14

    CPC classification number: G06F12/1441 ,  G06F12/1458

    Abstract: A processing system includes a communication system and a processing core configured to generate write requests. A circuit has associated a slave interface circuit configured to manage an address sub-range and selectively forward write requests addressed to a given address. Configuration data specifies whether the given address is protected/unprotected and locked/unlocked. In response to a received write request, address and data are extracted and a determination based on the configuration data is made as to whether the extracted address is protected/unprotected, and locked/unlocked. When the extracted address is unprotected or unlocked, the slave interface forwards the write request. When the extracted address is protected and locked, the slave interface generates an unlock signal in response to a comparison of the extracted address with the extracted data, with the unlock signal being asserted when the extracted data satisfy a predetermined rule with respect to the extracted address.

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