公开(公告)号：US11923248B2

公开(公告)日：2024-03-05

申请号：US17861450

申请日：2022-07-11

Applicant: GLOBALFOUNDRIES U.S. INC.

Inventor： Hui Zang ,  Ruilong Xie

IPC: H01L21/8238 ,  H01L21/768 ,  H01L21/8234 ,  H01L27/088 ,  H01L29/66 ,  H01L29/78

CPC classification number: H01L21/823437 ,  H01L21/76831 ,  H01L21/823431 ,  H01L27/0886 ,  H01L29/66545 ,  H01L29/66795 ,  H01L29/785

Abstract: The present disclosure relates to semiconductor structures and, more particularly, to a single diffusion cut for gate structures and methods of manufacture. The structure includes: a plurality of fin structures; a plurality of gate structures extending over the plurality of fin structures; a plurality of diffusion regions adjacent to the each of the plurality of gate structures; a single diffusion break between the diffusion regions of the adjacent gate structures; and a liner separating the single diffusion break from the diffusion regions.

公开(公告)号：US20240072180A1

公开(公告)日：2024-02-29

申请号：US17896711

申请日：2022-08-26

Applicant: GlobalFoundries U.S. Inc.

Inventor： Saloni Chaurasia ,  Jeffrey Johnson ,  Vibhor Jain ,  Crystal R. Kenney ,  Sudesh Saroop ,  Teng-Yin Lin ,  John J. Pekarik

IPC: H01L29/93 ,  H01L29/10 ,  H01L29/66

CPC classification number: H01L29/93 ,  H01L29/1095 ,  H01L29/66174

Abstract: Structures for a varactor diode and methods of forming same. The structure comprises a first semiconductor layer including a section on a substrate, a second semiconductor layer on the section of the first semiconductor layer, a third semiconductor layer on the second semiconductor layer, and a doped region in the section of the first semiconductor layer. The section of the first semiconductor layer and the doped region have a first conductivity type, and the second semiconductor layer comprises silicon-germanium having a second conductivity type opposite to the first conductivity type, and the third semiconductor layer has the second conductivity type. The doped region contains a higher concentration of a dopant of the first conductivity type than the section of the first semiconductor layer. The second semiconductor layer abuts the first section of the first semiconductor layer along an interface, and the doped region is positioned adjacent to the interface.

公开(公告)号：US20240068879A1

公开(公告)日：2024-02-29

申请号：US17896823

申请日：2022-08-26

Applicant: GlobalFoundries U.S. Inc.

Inventor： Zhixing ZHAO ,  Yiching CHEN

IPC: G01K7/01

CPC classification number: G01K7/01

Abstract: The present disclosure relates to semiconductor structures and, more particularly, to built-in temperature sensors and methods of manufacture and operation. The structure includes: a semiconductor on insulator substrate; an insulator layer under the semiconductor on the insulator substrate; a handle substrate under insulator layer; a first well of a first dopant type in the handle substrate; a second well of a second dopant type in the handle substrate, adjacent to the first well; and a back-gate diode at a juncture of the first well and the second well.

公开(公告)号：US11913971B2

公开(公告)日：2024-02-27

申请号：US17183432

申请日：2021-02-24

Applicant: GLOBALFOUNDRIES U.S. Inc.

Inventor： Romain H. A. Feuillette ,  David C. Pritchard ,  Elizabeth Strehlow ,  James P. Mazza

IPC: G01P15/00 ,  G01C9/24 ,  G01C9/06 ,  G01C9/20 ,  G01P15/18 ,  G01C9/18

CPC classification number: G01P15/006 ,  G01C9/06 ,  G01C9/20 ,  G01C9/24 ,  G01P15/18 ,  G01C2009/182

Abstract: Disclosed are a motion-sensitive field effect transistor (MSFET), a motion detection system, and a method. The MSFET includes a gate structure with a reservoir containing conductive fluid and gate electrode(s). Given position(s) of the gate electrode(s) and a fill level of the fluid within the reservoir, contact between the gate electrode(s) and the fluid depends upon the orientation the MSFET channel region relative to the top surface of the conductive fluid and the orientation of the MSFET channel region relative to the top surface of the conductive fluid depends upon position in space and/or movement of the MSFET and, particularly, position in space and/or movement of the chip on which the MSFET is formed. An electrical property of the MSFET in response to specific bias conditions varies depending on whether or not or to what extent the gate electrode(s) contact the fluid and is, thus, measurable for sensing chip motion.

公开(公告)号：US20240063309A1

公开(公告)日：2024-02-22

申请号：US17892205

申请日：2022-08-22

Applicant: GlobalFoundries U.S. Inc.

Inventor： Francois Hebert ,  James A. Cooper

IPC: H01L29/808 ,  H01L29/16 ,  H01L29/66

CPC classification number: H01L29/808 ,  H01L29/1608 ,  H01L29/66068

Abstract: Structures for a junction field-effect transistor and methods of forming such structures. The structure comprises a semiconductor substrate including a trench, and a source including a doped region in the semiconductor substrate adjacent to the trench. The doped region and the semiconductor substrate have the same conductivity type. The doped region has a first boundary adjacent to a surface of the semiconductor substrate and a second boundary spaced in depth from the first boundary. The structure further comprises a gate structure including a conductor layer inside the trench and a dielectric layer inside the trench. The first conductor layer has a surface positioned between the first boundary of the doped region and the second boundary of the doped region, and the dielectric layer is positioned on the surface of the conductor layer.

公开(公告)号：US20240063225A1

公开(公告)日：2024-02-22

申请号：US17820248

申请日：2022-08-17

Applicant: GLOBALFOUNDRIES U.S. Inc.

Inventor： DAVID PRITCHARD ,  HONGRU REN ,  SHAFIULLAH SYED ,  HONG YU ,  MAN GU ,  JIANWEI PENG

IPC: H01L27/12 ,  H01L21/84

CPC classification number: H01L27/1207 ,  H01L21/84

Abstract: A substrate is provided. The substrate includes a base, a semiconductor layer over the base, and an insulator layer between the base and the semiconductor layer. The semiconductor layer has a first semiconductor layer portion having a first thickness, a second semiconductor layer portion having a second thickness, and a third semiconductor layer portion having a third thickness, and the first thickness, the second thickness, and the third thickness are different from each other.

公开(公告)号：US20240063219A1

公开(公告)日：2024-02-22

申请号：US17819980

申请日：2022-08-16

Applicant: GlobalFoundries U.S. Inc.

Inventor： Santosh Sharma ,  Jerry Joseph James ,  Steven J. Bentley ,  Francois Hebert ,  Richard J. Rassel

IPC: H01L27/088 ,  H01L29/66 ,  H01L29/778 ,  H01L29/40 ,  H01L29/06

CPC classification number: H01L27/0883 ,  H01L29/66462 ,  H01L29/7786 ,  H01L29/401 ,  H01L29/402 ,  H01L29/0607

Abstract: A structure for an III-V integrated circuit includes an integrated depletion and enhancement mode gallium nitride high electron mobility transistors (HEMTs). The structure includes a first, depletion mode HEMT having a first source, a first drain and a first fieldplate gate between the first source and the first drain, and a second, enhancement mode HEMT having a second source and a second drain. The second HEMT also includes a gallium nitride (GaN) gate and a second fieldplate gate between the second source and the second drain. The second fieldplate gate of the second HEMT may be closer to the second drain than the GaN gate. The structure provides a reliable, low leakage, high voltage depletion mode HEMT (e.g., with operating voltages of greater than 100V, but with a pinch-off voltage of less than 6 Volts) integrated with a gallium nitride (GaN) gate-based enhancement mode HEMT.

公开(公告)号：US11908857B2

公开(公告)日：2024-02-20

申请号：US16901417

申请日：2020-06-15

Applicant: GLOBALFOUNDRIES U.S. Inc.

Inventor： Yanping Shen ,  Haiting Wang ,  Sipeng Gu

IPC: H01L27/088 ,  H01L21/8234 ,  H01L21/8238

CPC classification number: H01L27/0886 ,  H01L21/823437 ,  H01L21/823468 ,  H01L21/823481 ,  H01L21/823878

Abstract: Structures for a semiconductor device that include dielectric isolation and methods of forming a structure for a semiconductor device that includes dielectric isolation. A semiconductor body includes a cavity, first and second gate structures extending over the semiconductor body, and a semiconductor layer including first and second sections on the semiconductor body. The first section of the semiconductor layer is laterally positioned between the cavity and the first gate structure, and the second section on the semiconductor layer is laterally positioned between the cavity and the second gate structure. An isolation structure is laterally positioned between the first and second sections of the semiconductor layer. The isolation structure includes a dielectric layer and a sidewall spacer having first and second sections. The dielectric layer includes a first portion in the cavity and a second portion between the first and second sections of the sidewall spacer.

公开(公告)号：US11906451B2

公开(公告)日：2024-02-20

申请号：US17448081

申请日：2021-09-20

Applicant: Nova Ltd. ,  GLOBALFOUNDRIES U.S. INC.

Inventor： Wei Ti Lee ,  Heath A. Pois ,  Mark Klare ,  Cornel Bozdog ,  Alok Vaid

IPC: G01N23/2273 ,  H01L21/66 ,  G01B11/06 ,  G01B15/02 ,  G01N23/2208 ,  G01N23/223

CPC classification number: G01N23/2273 ,  G01B11/06 ,  G01B15/02 ,  G01N23/223 ,  G01N23/2208 ,  H01L22/12 ,  G01N2223/305 ,  G01N2223/61 ,  G01N2223/633

Abstract: A monitoring system and method are provided for determining at least one property of an integrated circuit (IC) comprising a multi-layer structure formed by at least a layer on top of an underlayer. The monitoring system receives measured data comprising data indicative of optical measurements performed on the IC, data indicative of x-ray photoelectron spectroscopy (XPS) measurements performed on the IC and data indicative of x-ray fluorescence spectroscopy (XRF) measurements performed on the IC. An optical data analyzer module analyzes the data indicative of the optical measurements and generates geometrical data indicative of one or more geometrical parameters of the multi-layer structure formed by at least the layer on top of the underlayer. An XPS data analyzer module analyzes the data indicative of the XPS measurements and generates geometrical and material related data indicative of geometrical and material composition parameters for said layer and data indicative of material composition of the underlayer. An XRF data analyzer module analyzes the data indicative of the XRF measurements and generates data indicative of amount of a predetermined material composition in the multi-layer structure. A data interpretation module generates combined data received from analyzer modules and processes the combined data and determines the at least one property of at least one layer of the multi-layer structure.

公开(公告)号：US20240045140A1

公开(公告)日：2024-02-08

申请号：US18378788

申请日：2023-10-11

Applicant: GLOBALFOUNDRIES U.S. INC.

Inventor： Yusheng BIAN ,  Ajey Poovannummoottil JACOB ,  Steven M. SHANK

IPC: G02B6/122 ,  G02B6/125 ,  G02B1/00

CPC classification number: G02B6/1225 ,  G02B6/125 ,  G02B1/002 ,  G02B1/005 ,  G02B2006/12061

Abstract: The present disclosure relates to semiconductor structures and, more particularly, to waveguide structures with metamaterial structures and methods of manufacture. The structure includes: at least one waveguide structure; and metamaterial structures separated from the at least one waveguide structure by an insulator material, the metamaterial structures being structured to decouple the at least one waveguide structure to simultaneously reduce insertion loss and crosstalk of the at least one waveguide structure.