公开(公告)号：US20020184221A1

公开(公告)日：2002-12-05

申请号：US10132675

申请日：2002-04-24

申请人： MOSAID Technologies, Inc.

发明人： Imtiaz Ahmad ,  David A. Brown

IPC分类号： G06F007/00 ,  G06F017/00

CPC分类号： H04L45/745 ,  Y10S707/99933 ,  Y10S707/99942 ,  Y10S707/99943 ,  Y10S707/99956

摘要： A load balancing mechanism maps a binary tree representation of a routing table into a set of fixed size memories. The mechanism efficiently utilizes the memory in the routing table without violating the tree precedence constraints and the memory access requirements of a pipelined system. The mechanism stores a subtree associated with a densely populated level of the binary tree in memory associated with lower levels.

摘要翻译： 负载平衡机制将路由表的二叉树表示映射到一组固定大小的存储器中。 该机制有效地利用路由表中的存储器，而不违反流优先级约束和流水线系统的存储器访问要求。 该机制将与二进制树的密集层次相关联的子树存储在与较低级别相关联的存储器中。

公开(公告)号：US20010044876A1

公开(公告)日：2001-11-22

申请号：US09733761

申请日：2000-12-08

申请人： Mosaid Technologies, Inc.

发明人： David A. Brown

IPC分类号： G06F012/00

CPC分类号： H04L45/742 ,  G06F17/30955 ,  G11C15/00 ,  H04L45/00 ,  H04L45/02 ,  H04L45/04 ,  H04L45/54 ,  H04L45/7453 ,  H04L45/7457 ,  Y10S707/99931 ,  Y10S707/99933 ,  Y10S707/99943

摘要： We present a lookup table which allows sparse subtree descriptors and dense subtree descriptors to be stored in the same memory. A subtree entry in the memory stores a dense subtree descriptor for a dense subtree or a plurality of sparse subtree descriptors for sparse subtrees. The subtree entry is indexed by a leaf in the previous subtree. The sparse subtree descriptor stores at least one node descriptor. The node descriptor describes a set of leaves in the sparse subtree having a common value. The common value is encoded in the node descriptor using run length encoding.

摘要翻译： 我们提出一个查找表，允许稀疏子树描述符和密集子树描述符存储在同一个存储器中。 存储器中的子树条目存储密集子树的密集子树描述符或稀疏子树的多个稀疏子树描述符。 子树条目由先前子树中的叶子索引。 稀疏子树描述符存储至少一个节点描述符。 节点描述符描述具有公共值的稀疏子树中的一组叶。 公共值使用运行长度编码在节点描述符中编码。

公开(公告)号：US20010042130A1

公开(公告)日：2001-11-15

申请号：US09733628

申请日：2000-12-08

申请人： Mosaid Technologies, Inc.

发明人： David A. Brown

IPC分类号： G06F015/173

CPC分类号： H04L45/742 ,  G06F16/902 ,  G11C15/00 ,  H04L45/00 ,  H04L45/02 ,  H04L45/04 ,  H04L45/54 ,  H04L45/7453 ,  H04L45/7457 ,  Y10S707/99931 ,  Y10S707/99933 ,  Y10S707/99943

摘要： We present a method and apparatus for increasing the depth of a lookup table. The lookup table includes at least two lookup units. A search request for a final result value corresponding to the key is issued to each of the lookup units in parallel. Each of the lookup units performs a multi-level search in parallel for the final result value. The final result value stored in only one of the lookup units is provided by one of the lookup units.

摘要翻译： 我们提出了一种增加查找表深度的方法和装置。 查找表包括至少两个查找单元。 与密钥对应的最终结果值的搜索请求并行发布给每个查找单元。 每个查找单元针对最终结果值并行执行多级搜索。 存储在仅一个查找单元中的最终结果值由查询单元之一提供。

公开(公告)号：US08023519B2

公开(公告)日：2011-09-20

申请号：US12612443

申请日：2009-11-04

申请人： David A. Brown ,  Peter B. Gillingham

发明人： David A. Brown ,  Peter B. Gillingham

IPC分类号： H04L12/28

CPC分类号： H04L45/00 ,  H04L45/7457

摘要： A lookup table for searching for a longest prefix match for a key is disclosed. The lookup table provides a match for a key in a single search cycle. The number of matches stored in the lookup table is maximized by storing each match in only one location in the lookup table. The binary tree is divided into a plurality of levels and each level has a plurality of subtrees. A subtree descriptor stored for a subtree includes a field for each node in the subtree. The state of the field indicates whether an entry for the node is stored in the table. The bit vector allows indexing of the single match stored for the key.

摘要翻译： 公开了一种用于搜索密钥的最长前缀匹配的查找表。 查找表提供了单个搜索周期中的键的匹配。 通过将每个匹配存储在查找表中的一个位置来最大化存储在查找表中的匹配数。 二叉树被分成多个级别，每个级别具有多个子树。 为子树存储的子树描述符包含子树中每个节点的字段。 该字段的状态指示节点的条目是否存储在表中。 位向量允许为密钥存储的单个匹配索引。

公开(公告)号：US07830877B2

公开(公告)日：2010-11-09

申请号：US11839184

申请日：2007-08-15

申请人： David A. Brown

发明人： David A. Brown

IPC分类号： H04L12/28

CPC分类号： H04L45/54 ,  G06F17/30949 ,  H04L47/21 ,  H04L49/205 ,  H04L49/3009 ,  H04L49/351

摘要： Management of congestion level, in a computer-related context, is disclosed. Also disclosed is a system generating a plurality of computer network-related tables during system operation. A number of the tables are each separately indexed by a different index. The system includes at least one tangible computer-readable medium adapted to store, at each indexed location, a swap count providing an indication of the congestion level of the indexed location. The system also includes insert logic stored as instructions on the at least one medium for execution. When executed, the insert logic is operable to: i) insert, when a predetermined condition has been satisfied, a new entry by overwriting the current entry stored in the indexed location having the lowest swap count; and ii) update the swap counts in each of the indexed locations in a manner that maintains the total swap count at least substantially constant over time.

摘要翻译： 在计算机相关的背景下披露拥塞程度的管理。 还公开了在系统操作期间生成多个计算机网络相关表的系统。 多个表分别由不同的索引分别索引。 该系统包括至少一个有形的计算机可读介质，其适于在每个索引的位置处存储提供索引位置的拥塞级别的指示的交换计数。 该系统还包括存储为用于执行的至少一个介质上的指令的插入逻辑。 当执行时，插入逻辑可操作为：i）当已经满足预定条件时，通过重写存储在具有最低交换次数的索引位置中的当前条目来插入新条目; 以及ii）以保持总交换计数至少基本上恒定的方式来更新每个索引位置中的交换计数。

公开(公告)号：US20090237981A1

公开(公告)日：2009-09-24

申请号：US12405153

申请日：2009-03-16

申请人： Valerie L. Lines

发明人： Valerie L. Lines

IPC分类号： G11C11/24 ,  G11C8/00

CPC分类号： G11C8/08 ,  G11C11/4085

摘要： A circuit which accurately controls the word line (pass transistor gate) driving voltage to a voltage which is both controlled and is not significantly greater than is needed to drive the word line. The circuit eliminates the need for a double-boot-strapping circuit, and ensures that no voltages exceed that necessary to fully turn on a memory cell access transistor. Voltages in excess of that which would reduce reliability are avoided, and accurate driving voltages are obtained. A DRAM includes word lines, memory cells having enable inputs connected to the word lines, a gate receiving word line selecting signals at first logic levels Vss and Vdd, and for providing a select signal at levels Vss and Vdd, a high voltage supply source Vpp which is higher in voltage than Vdd, a circuit for translating the select signals at levels Vss and Vdd to levels Vss and Vpp and for applying it directly to the word lines whereby an above Vdd voltage level word line is achieved without the use of double boot-strap circuits.

摘要翻译： 准确地将字线（传输晶体管栅极）驱动电压控制到电压的电路，该电压被控制并且不显着大于驱动字线所需的电压。 该电路消除了双引导电路的需要，并确保没有电压超过完全打开存储单元存取晶体管所需的电压。 避免超过降低可靠性的电压，并获得精确的驱动电压。 DRAM包括字线，具有连接到字线的使能输入的存储器单元，栅极接收字线以第一逻辑电平Vss和Vdd选择信号，以及用于提供电平Vss和Vdd的选择信号，高电压源Vpp 其电压高于Vdd，用于将电平Vss和Vdd的选择信号转换为电平Vss和Vpp并用于将其直接应用于字线的电路，由此实现上述Vdd电压电平字线而不使用双引导 - 电路。

公开(公告)号：US20090180483A1

公开(公告)日：2009-07-16

申请号：US12013148

申请日：2008-01-11

申请人： Steven A. Przybylski

发明人： Steven A. Przybylski

IPC分类号： H04L12/56

CPC分类号： H04L12/4637 ,  G06F13/4243 ,  H01L2224/32145 ,  H01L2224/48145 ,  H01L2224/48227 ,  H01L2224/73265 ,  H01L2924/15311 ,  H04L12/42 ,  Y02D10/14 ,  Y02D10/151 ,  H01L2224/32225 ,  H01L2924/00012

摘要： In a ring-of-clusters network topology, groups of slave devices are accessed in parallel, such that the latency around the ring is proportional to the number of clusters and not proportional to the number of integrated circuits. The devices of a cluster share input and output ring segments such that packets arriving on the input segment are received and interpreted by all the devices in a cluster. In other embodiments, none, some or all but one slaves per cluster are asleep or otherwise disabled so that they do not input and interpret incoming packets. Regardless, in all embodiments, the slaves of a cluster cooperate, potentially under the controller's direction, to ensure that at most one of them is actively driving the output segment at any given time. The devices may be addressed through a device ID, a cluster ID, or a combination thereof. Embodiments of the invention are suited to exploit multi-chip module implementations and forms of vertical circuit stacking.

摘要翻译： 在集群中的网络拓扑结构中，并行访问从属设备组，使得环周围的延迟与集群的数量成比例，与集成电路的数量成正比。 集群的设备共享输入和输出环段，使得到达输入段的数据包被集群中的所有设备接收和解释。 在其他实施例中，每个群集中的一个或全部除了一个从设备是睡着的或者被禁用的，使得它们不输入和解释传入的分组。 无论如何，在所有实施例中，集群的从站可能在控制器的方向下协作，以确保其中至少一个在任何给定时间主动地驱动输出段。 可以通过设备ID，集群ID或其组合来寻址设备。 本发明的实施例适用于利用多芯片模块实现和垂直电路堆叠的形式。

公开(公告)号：US07532050B2

公开(公告)日：2009-05-12

申请号：US11906872

申请日：2007-10-04

申请人： Dieter Haerle ,  Tony Mai ,  Peter Vlasenko

发明人： Dieter Haerle ,  Tony Mai ,  Peter Vlasenko

IPC分类号： H03L7/06

CPC分类号： H03L7/08 ,  H03L7/0812 ,  H03L7/0891 ,  H03L7/0895 ,  H03L7/095 ,  H03L7/10

摘要： A delay locked loop includes initialization circuitry that ensures that a DLL is initialized to an operating point that is not to close to either end of a delay vs. control voltage characteristic. The initialization circuitry forces the DLL to initially search for a lock point starting from an initial delay, the delay is varied in one direction, forcing the DLL to skip the first lock point. The initialization circuitry only allows the DLL to vary the delay of the voltage controlled delay loop in the one direction from the initial delay until the operating point is reached.

摘要翻译： 延迟锁定环包括初始化电路，其确保将DLL初始化为不接近延迟与控制电压特性的任一端的工作点。 初始化电路强制DLL最初从初始延迟开始搜索锁定点，延迟在一个方向上变化，迫使DLL跳过第一个锁定点。 初始化电路仅允许DLL改变从初始延迟到达到工作点的一个方向的电压控制延迟环的延迟。

公开(公告)号：US20090086876A1

公开(公告)日：2009-04-02

申请号：US12315289

申请日：2008-12-02

申请人： Tony Mai

发明人： Tony Mai

IPC分类号： H03D3/24

CPC分类号： H03L7/10 ,  H03L7/0812 ,  H03L7/0891

摘要： An initialization circuit in a delay locked loop ensures that after power up or other reset clock edges are received by a phase detector in the appropriate order for proper operation. After reset of the delay locked loop, the initialization circuit assures that at least one edge of a reference clock is received prior to enabling the phase detector to increase (or decrease) the delay in a delay line. After at least one edge of a feedback clock is received, the initialization circuit enables the phase detector to decrease (or increase) the delay in a delay line.

摘要翻译： 延迟锁定环路中的初始化电路确保上电或其他复位时钟沿由相位检测器以适当的顺序以适当的顺序接收。 在延迟锁定环路复位之后，初始化电路确保在使相位检测器增加（或减小）延迟线中的延迟之前，接收到参考时钟的至少一个边沿。 在接收到反馈时钟的至少一个边缘之后，初始化电路使相位检测器能够减小（或增加）延迟线中的延迟。

公开(公告)号：US20090073792A1

公开(公告)日：2009-03-19

申请号：US12221195

申请日：2008-07-31

申请人： Richard C. Foss

发明人： Richard C. Foss

IPC分类号： G11C7/06

CPC分类号： G11C7/1069 ,  G11C7/06 ,  G11C7/1048 ,  G11C7/1051 ,  G11C11/4091 ,  G11C11/4093 ,  G11C11/4096 ,  G11C11/4097 ,  G11C2207/002 ,  G11C2207/005

摘要： A dynamic random access memory (DRAM) having pairs of bitlines, each pair being connected to a first bit line sense amplifier, wordlines crossing the bitlines pairs forming an array, charge storage cells connected to the bitlines, each having an enable input connected to a wordline, the bit line sense amplifiers being connected in a two dimensional array, pairs of primary databuses being connected through first access transistors to plural corresponding bit line sense amplifiers in each row of the array, apparatus for enabling columns of the first access transistors, databus sense amplifiers each connected to a corresponding data bus pair, a secondary databus, the secondary databus being connected through second access transistors to the databus sense amplifiers, and apparatus for enabling the second access transistors, whereby each the primary databus pair may be shared by plural sense amplifiers in a corresponding row of the array and the secondary databus may be shared by plural primary databus pairs.