公开(公告)号：US11769954B2

公开(公告)日：2023-09-26

申请号：US17001451

申请日：2020-08-24

申请人： TENSORCOM, INC.

发明人： Guang-Fu Cheng

IPC分类号： H01Q21/06 ,  H01Q1/48 ,  H01Q21/00 ,  H01Q1/38 ,  H01Q1/24

CPC分类号： H01Q21/067 ,  H01Q1/38 ,  H01Q1/48 ,  H01Q21/0006 ,  H01Q21/0087 ,  H01Q1/241

摘要： An antenna array system and a method for making the antenna system. The system includes at least two antenna elements serving as transmitter elements, and at least two antenna elements serving as receiver elements. Each of the transmitter antenna and receiver antenna elements include a pair of curved arms, wherein a first arm in the pair of curved arms is configured to be connected from a signal trace of the antenna system. The second arm in the pair of curved arms is configured to be connected to a ground plane.

公开(公告)号：US10778250B2

公开(公告)日：2020-09-15

申请号：US16277890

申请日：2019-02-15

申请人： TensorCom, Inc.

发明人： Bo Xia ,  Ricky Lap Kei Cheung ,  Bo Lu

IPC分类号： H03M13/11

摘要： Processors are arranged in a pipeline structure to operate on multiple layers of data, each layer comprising multiple groups of data. An input to a memory is coupled to an output of the last processor in the pipeline, and the memory's output is coupled to an input of the first processor in the pipeline. Multiplexing and de-multiplexing operations are performed in the pipeline. For each group in each layer, a stored result read from the memory is applied to the first processor in the pipeline structure. A calculated result of the stored result is output at the last processor and stored in the memory. Once processing for the last group of data in a first layer is completed, the corresponding processor is configured to process data in a next layer before the pipeline finishes processing the first layer. The stored result obtained from the next layer comprises a calculated result produced from a layer previous to the first layer.

公开(公告)号：US10250280B2

公开(公告)日：2019-04-02

申请号：US15011252

申请日：2016-01-29

申请人： Tensorcom, Inc.

发明人： Bo Xia ,  Ricky Lap Kei Cheung ,  Bo Lu

IPC分类号： H03M13/11

摘要： Processors are arranged in a pipeline structure to operate on multiple layers of data, each layer comprising multiple groups of data. An input to a memory is coupled to an output of the last processor in the pipeline, and the memory's output is coupled to an input of the first processor in the pipeline. Multiplexing and de-multiplexing operations are performed in the pipeline. For each group in each layer, a stored result read from the memory is applied to the first processor in the pipeline structure. A calculated result of the stored result is output at the last processor and stored in the memory. Once processing for the last group of data in a first layer is completed, the corresponding processor is configured to process data in a next layer before the pipeline finishes processing the first layer. The stored result obtained from the next layer comprises a calculated result produced from a layer previous to the first layer.

公开(公告)号：US20170310308A1

公开(公告)日：2017-10-26

申请号：US15646776

申请日：2017-07-11

申请人： Tensorcom, Inc.,

发明人： Zaw Soe ,  KhongMeng Tham

IPC分类号： H03K3/012 ,  H03K17/56 ,  H01Q1/50 ,  H04B5/00 ,  G05F3/16

CPC分类号： H03K3/012 ,  G05F3/16 ,  H01Q1/50 ,  H03K17/56 ,  H04B5/0075

摘要： This invention eliminates the need for “capacitor coupling” or “transformer coupling,” and the associated undesirable parasitic capacitance and inductance associated with these coupling techniques when designing high frequency (˜60 GHz) circuits. At this frequency, the distance between two adjacent stages needs to be minimized. A resonant circuit in series with the power or ground leads is used to isolate a biasing signal from a high frequency signal. The introduction of this resonant circuit allows a first stage to be “directly coupled” to a next stage using a metallic trace. The “direct coupling” technique passes both the high frequency signal and the biasing voltage to the next stage. The “direct coupling” approach overcomes the large die area usage when compared to either the “AC coupling” or “transformer coupling” approach since neither capacitors nor transformers are required to transfer the high frequency signals between stages.

公开(公告)号：US20170126464A1

公开(公告)日：2017-05-04

申请号：US15357566

申请日：2016-11-21

申请人： Tensorcom, Inc.

发明人： Zaw Soe

IPC分类号： H04L27/38 ,  H03D7/14 ,  H03F3/45 ,  H03F1/22 ,  H03F3/193 ,  H03F1/42 ,  H03D7/16

CPC分类号： H03F1/42 ,  H03D7/125 ,  H03D7/1441 ,  H03D7/1466 ,  H03D7/165 ,  H03F1/223 ,  H03F3/193 ,  H03F3/387 ,  H03F3/45071 ,  H03F3/45179 ,  H03F2200/108 ,  H03F2200/294 ,  H03F2200/451 ,  H03F2200/492 ,  H03F2200/72 ,  H03F2200/75 ,  H04L27/38

摘要： A receiver comprises a Low Noise Amplifier (LNA) configured to amplify an input signal and a resonant circuit coupled to the LNA. A first switch couples current from the resonant circuit to a first capacitor integrating a first voltage, wherein the first switch is enabled with a clock signal. A second switch couples current from the resonant circuit to a second capacitor integrating a second voltage, wherein the second switch is enabled with an inverse clock signal. A differential amplifier comprises a positive input for receiving the first voltage and a negative input for receiving the second voltage in order to produce a sum and a difference frequency spectrum between a signal spectrum carried within the current and a frequency of the clock signal.

公开(公告)号：US20160134293A1

公开(公告)日：2016-05-12

申请号：US14995471

申请日：2016-01-14

申请人： Tensorcom, Inc.

发明人： Dai Dai

IPC分类号： H03M1/00 ,  H03M1/18 ,  H03M1/08 ,  H03H11/48 ,  H03K5/24

CPC分类号： H03K5/2481 ,  H03H11/481 ,  H03M1/002 ,  H03M1/0836 ,  H03M1/0845 ,  H03M1/183

摘要： A negative-capacitance circuit comprises a first node coupled to a drain of a first transistor and a gate of a second transistor; a second node coupled to a drain of the second transistor and a gate of the first transistor; a capacitor coupled between a source of the first transistor and a source of the second transistor; a first current mirror coupled between a supply voltage and the source of the first transistor; and a second current mirror coupled between the supply voltage and the source of the second transistor. The circuit can be configured to drive the differential capacitive load between the first and second nodes in a shorter time period, thereby increasing the transfer bandwidth of the differential signal.

摘要翻译： 负电容电路包括耦合到第一晶体管的漏极和第二晶体管的栅极的第一节点; 耦合到所述第二晶体管的漏极和所述第一晶体管的栅极的第二节点; 耦合在所述第一晶体管的源极和所述第二晶体管的源极之间的电容器; 耦合在电源电压和第一晶体管的源极之间的第一电流镜; 以及耦合在电源电压和第二晶体管的源极之间的第二电流镜。 该电路可被配置为在较短时间段内驱动第一和第二节点之间的差分电容性负载，从而增加差分信号的传输带宽。

公开(公告)号：US09287836B2

公开(公告)日：2016-03-15

申请号：US14108312

申请日：2013-12-16

申请人： Tensorcom, Inc.

发明人： Zaw Soe

IPC分类号： H04B1/16 ,  H03F3/19 ,  H03F3/387 ,  H03F1/22 ,  H03F3/193 ,  H03D7/12 ,  H03D7/14 ,  H03D7/16

CPC分类号： H03F1/42 ,  H03D7/125 ,  H03D7/1441 ,  H03D7/1466 ,  H03D7/165 ,  H03F1/223 ,  H03F3/193 ,  H03F3/387 ,  H03F3/45071 ,  H03F3/45179 ,  H03F2200/108 ,  H03F2200/294 ,  H03F2200/451 ,  H03F2200/492 ,  H03F2200/72 ,  H03F2200/75 ,  H04L27/38

摘要： A cascode common source and common gate LNAs operating at 60 GHz are introduced and described. The cascode common source LNA is simulated to arrive at an optimum ratio of upper device width to the lower device width. The voltage output of the cascode common source LNA is translated into a current to feed and apply energy to the mixer stage. These input current signals apply the energy associated with the current directly into the switched capacitors in the mixer to minimize the overall power dissipation of the system. The LNA is capacitively coupled to the mixer switches in the I and Q mixers and are enabled and disabled by the clocks generated by the quadrature oscillator. These signals are then amplified by a differential amplifier to generate the sum and difference frequency spectra.

摘要翻译： 引入并描述了以60GHz操作的共源共栅和公共栅极LNA。 对共源共栅源LNA进行模拟，以达到上部器件宽度与较低器件宽度的最佳比例。 共源共栅源LNA的电压输出转换为电流以馈送并将能量施加到混频器级。 这些输入电流信号将与电流相关联的能量直接施加到混频器中的开关电容器中，以最小化系统的总功耗。 LNA电容耦合到I和Q混频器中的混频器开关，并由正交振荡器产生的时钟使能和禁止。 然后，这些信号被差分放大器放大以产生和和差频谱。

公开(公告)号：US09197222B2

公开(公告)日：2015-11-24

申请号：US14108329

申请日：2013-12-16

申请人： Tensorcom, Inc.

发明人： Syed Enam Rehman

IPC分类号： H03B5/08 ,  H03L7/00 ,  H03L1/02 ,  H03B1/00 ,  H03L7/18 ,  H03B5/12

CPC分类号： H03L7/00 ,  H03B1/00 ,  H03B5/1212 ,  H03B5/1228 ,  H03B5/1243 ,  H03B5/1265 ,  H03B2200/0062 ,  H03L1/023 ,  H03L7/18

摘要： Capacitive adjustment in an RCL resonant circuit is typically performed by adjusting a DC voltage being applied to one side of the capacitor. One side of the capacitor is usually connected to either the output node or the gate of a regenerative circuit in an RCL resonant circuit. The capacitance loading the resonant circuit becomes a function of the DC voltage and the AC sinusoidal signal generated by the resonant circuit. By capacitively coupling both nodes of the capacitor, a DC voltage can control the value of the capacitor over the full swing of the output waveform. In addition, instead of the RCL resonant circuit driving a single differential function loading the outputs, each output drives an independent single ended function; thereby providing two simultaneous operations being determined in place of the one differential function.

摘要翻译： RCL谐振电路中的电容调整通常通过调整施加到电容器一侧的直流电压来进行。 电容器的一侧通常连接到RCL谐振电路中的再生电路的输出节点或栅极。 谐振电路的电容成为由谐振电路产生的直流电压和交流正弦信号的函数。 通过电容耦合电容器的两个节点，DC电压可以在输出波形的全摆幅时控制电容器的值。 此外，代替RCL谐振电路驱动负载输出的单个差分功能，每个输出驱动独立的单端功能; 从而提供两个同时的操作来代替一个差分功能。

公开(公告)号：US09124279B2

公开(公告)日：2015-09-01

申请号：US13602216

申请日：2012-09-03

申请人： Dai Dai

发明人： Dai Dai

IPC分类号： H03H11/46 ,  H03F3/45 ,  H03M1/00 ,  H03K5/24 ,  H03M1/08 ,  H03M1/18 ,  H03H11/48

CPC分类号： H03K5/2481 ,  H03H11/481 ,  H03M1/002 ,  H03M1/0836 ,  H03M1/0845 ,  H03M1/183

摘要： The differential output of a Programmable Gain Amplifier (PGA) is loaded by the input differential gate capacitance of a plurality of Analog to Digital converters (ADC) comparators and the differential metal layer traces to interconnect these comparators to the PGA. The differential capacitive load presented to the PGA is quite large and reduces the bandwidth of this interconnect between the PGA and ADC. To overcome the performance degradation due to the differential capacitive load, an active negative-capacitor circuit cancels the effect of the large input capacitance of the ADC comparators. This cancellation extends the gain characteristics of the interconnect between the PGA's output and the inputs of the first stage of the comparators. The active negative-capacitance is comprised of a cross pair NMOS with a capacitor connecting their sources where each NMOS is biased by a current source.

摘要翻译： 可编程增益放大器（PGA）的差分输出由多个模数转换器（ADC）比较器的输入差分栅极电容和差分金属层迹线加载，以将这些比较器与PGA互连。 提供给PGA的差分电容性负载相当大，并降低了PGA和ADC之间的这种互连的带宽。 为了克服由于差分电容性负载引起的性能下降，有源负电容电路消除了ADC比较器的大输入电容的影响。 这种消除延长了PGA输出与比较器的第一级的输入之间的互连的增益特性。 有源负电容由交叉对NMOS构成，其中电容器连接其源极，其中每个NMOS由电流源偏置。

公开(公告)号：US08884713B2

公开(公告)日：2014-11-11

申请号：US13474742

申请日：2012-05-18

申请人： KhongMeng Tham

发明人： KhongMeng Tham

IPC分类号： H03B5/08

CPC分类号： H03B1/04 ,  H03B5/1212 ,  H03B5/1228 ,  H03B2202/04 ,  H03B2202/088

摘要： This invention compensates for the unintentional magnetic coupling between a first and second inductor of two different closely spaced inductors separated by a conversion circuit. A cancellation circuit formed from transistors senses the magnetic coupling in the first inductor and feeds a current opposite to the induced magnetic coupling captured by the second inductor such that the coupled magnetic coupling can be compensated and allows the first and second inductors to behave independently with regards to the coupled magnetic coupling between the first and second inductors. This allows the distance between the first and second inductors to be minimized which saves silicon area. In addition, the performance is improved since the overall capacitance in both circuits can be decreased. This cancellation technique to reduce the magnetic coupling between two closed placed inductively loaded circuits allows the design of a more compact and faster performing circuit.

摘要翻译： 本发明补偿由转换电路分离的两个不同紧密间隔的电感器的第一和第二电感器之间的无意的磁耦合。 由晶体管形成的消除电路感测第一电感器中的磁耦合，并且馈送与由第二电感器捕获的感应磁耦合相反的电流，使得耦合的磁耦合可以被补偿，并允许第一和第二电感器独立地表现， 耦合到第一和第二电感器之间的耦合磁耦合。 这允许第一和第二电感器之间的距离最小化，从而节省了硅面积。 此外，由于可以降低两个电路中的整体电容，性能得到改善。 这种减少两个闭合放置的感应加载电路之间的磁耦合的消除技术允许设计更紧凑和更快的执行电路。