公开(公告)号：US20090061644A1

公开(公告)日：2009-03-05

申请号：US12013759

申请日：2008-01-14

Applicant: Tony P. Chiang ,  Sunil Shanker ,  Chi I. Lang

Inventor： Tony P. Chiang ,  Sunil Shanker ,  Chi I. Lang

IPC: H01L21/31 ,  B05C11/00

CPC classification number: C23C16/45574 ,  C23C16/45544 ,  C23C16/45548

Abstract: A combinatorial processing chamber and method are provided. In the method a fluid volume flows over a surface of a substrate with differing portions of the fluid volume having different constituent components to concurrently expose segregated regions of the substrate to a mixture of the constituent components that differ from constituent components to which adjacent regions are exposed. Differently processed segregated regions are generated through the multiple flowings.

公开(公告)号：US07482245B1

公开(公告)日：2009-01-27

申请号：US11471958

申请日：2006-06-20

Applicant: Jengyi Yu ,  Chi-I Lang ,  Judy H. Huang

Inventor： Jengyi Yu ,  Chi-I Lang ,  Judy H. Huang

IPC: H01L21/76

CPC classification number: H01L21/823807 ,  H01L21/823878 ,  H01L29/665 ,  H01L29/78 ,  H01L29/7846

Abstract: High density plasma (HDP) techniques form silicon oxide films having sequentially modulated stress profiles. The HDP techniques use low enough temperatures to deposit silicon oxide films in transistor architectures and fabrication processes effective for generating channel strain without adversely impacting transistor integrity. Methods involve partially filling a trench on a substrate with a portion of deposited dielectric using a high density plasma chemical vapor deposition process. The conditions of the process are configured to produce a first stress condition in the first portion of the deposited dielectric. The deposition process condition may then be modified to produce a different stress condition in deposited dielectric. The partially-filled trench may be further filled using the modified deposition process to produce additional dielectric and can be repeated until the trench is filled. Transistor strain can be generated in NMOS or PMOS devices using stress profile modulation in STI gap fill.

Abstract translation: 高密度等离子体（HDP）技术形成具有顺序调制应力分布的氧化硅膜。 HDP技术使用足够低的温度以在晶体管架构和制造工艺中沉积氧化硅膜，其有效地用于产生通道应变而不会不利地影响晶体管的完整性。 方法涉及使用高密度等离子体化学气相沉积工艺在一部分沉积的电介质上部分填充衬底上的沟槽。 该过程的条件被配置为在沉积的电介质的第一部分中产生第一应力状态。 然后可以修改沉积工艺条件以在沉积的电介质中产生不同的应力条件。 可以使用改进的沉积工艺进一步填充部分填充的沟槽，以产生额外的电介质并且可以重复直到填充沟槽。 晶体管应变可以在使用STI间隙填充中的应力分布调制的NMOS或PMOS器件中产生。

公开(公告)号：US20080220601A1

公开(公告)日：2008-09-11

申请号：US11714334

申请日：2007-03-05

Applicant: Nitin Kumar ,  Jinhong Tong ,  Chi-I Lang ,  Tony Chiang ,  Prashant B. Phatak

Inventor： Nitin Kumar ,  Jinhong Tong ,  Chi-I Lang ,  Tony Chiang ,  Prashant B. Phatak

IPC: H01L21/20 ,  H01L21/4763

CPC classification number: H01L45/04 ,  H01L27/2463 ,  H01L45/1233 ,  H01L45/1253 ,  H01L45/146 ,  H01L45/1608

Abstract: Nonvolatile memory elements are provided that have resistive switching metal oxides. The nonvolatile memory elements may be formed by depositing a metal-containing material on a silicon-containing material. The metal-containing material may be oxidized to form a resistive-switching metal oxide. The silicon in the silicon-containing material reacts with the metal in the metal-containing material when heat is applied. This forms a metal silicide lower electrode for the nonvolatile memory element. An upper electrode may be deposited on top of the metal oxide. Because the silicon in the silicon-containing layer reacts with some of the metal in the metal-containing layer, the resistive-switching metal oxide that is formed is metal deficient when compared to a stoichiometric metal oxide formed from the same metal.

Abstract translation: 提供具有电阻开关金属氧化物的非易失性存储元件。 非易失性存储元件可以通过将含金属的材料沉积在含硅材料上而形成。 含金属材料可以被氧化以形成电阻式开关金属氧化物。 当施加热量时，含硅材料中的硅与含金属材料中的金属反应。 这形成用于非易失性存储元件的金属硅化物下电极。 上部电极可以沉积在金属氧化物的顶部。 由于含硅层中的硅与含金属层中的一些金属反应，与由相同金属形成的化学计量的金属氧化物相比，形成的电阻 - 开关金属氧化物是金属缺陷的。

公开(公告)号：US07211525B1

公开(公告)日：2007-05-01

申请号：US11082369

申请日：2005-03-16

Applicant: Sunil Shanker ,  Sean Cox ,  Chi-I Lang ,  Judy H. Huang ,  Minh Anh Nguyen ,  Ken Vo ,  Wenxian Zhu

Inventor： Sunil Shanker ,  Sean Cox ,  Chi-I Lang ,  Judy H. Huang ,  Minh Anh Nguyen ,  Ken Vo ,  Wenxian Zhu

IPC: H01L21/469 ,  H01L21/31

CPC classification number: H01L21/31612 ,  C23C16/0245 ,  H01L21/02164 ,  H01L21/02274 ,  H01L21/0228 ,  H01L21/02315 ,  H01L21/76224 ,  H01L21/76837

Abstract: Methods of filling gaps on semiconductor substrates with dielectric film are described. The methods reduce or eliminate sidewall deposition and top-hat formation. The methods also reduce or eliminate the need for etch steps during dielectric film deposition. The methods include treating a semiconductor substrate with a hydrogen plasma before depositing dielectric film on the substrate. In some embodiments, the hydrogen treatment is used is conjunction with a high rate deposition process.

Abstract translation: 描述了用绝缘膜填充半导体衬底上的间隙的方法。 该方法减少或消除侧壁沉积和顶帽形成。 在电介质膜沉积期间，这些方法还减少或消除了蚀刻步骤的需要。 所述方法包括在沉积介质膜之前用氢等离子体处理半导体衬底。 在一些实施方案中，使用氢处理与高速沉积工艺相结合。

公开(公告)号：US08683420B2

公开(公告)日：2014-03-25

申请号：US12948257

申请日：2010-11-17

Applicant: Yun Wang ,  Tony P. Chiang ,  Ryan Clarke ,  Chi-I Lang ,  Yoram Schwarz

Inventor： Yun Wang ,  Tony P. Chiang ,  Ryan Clarke ,  Chi-I Lang ,  Yoram Schwarz

IPC: G06F17/50

CPC classification number: H01L22/14

Abstract: A method and system of improved reliability testing includes providing a first substrate and a second substrate, each substrate comprising only a first metallization layer; processing regions on a first substrate by combinatorially varying at least one of materials, unit processes, and process sequences; performing a first reliability test on the processed regions on the first substrate to generate first results; processing regions on a second substrate in a combinatorial manner by varying at least one of materials, unit processes, and process sequences based on the first results of the first reliability test; performing a second reliability test on the processed regions on the second substrate to generate second results; and determining whether the first substrate and the second substrate meet a predetermined quality threshold based on the second results.

Abstract translation: 改进的可靠性测试的方法和系统包括提供第一衬底和第二衬底，每个衬底仅包括第一金属化层; 通过组合地改变材料，单元过程和工艺顺序中的至少一个来处理第一衬底上的处理区域; 对所述第一基板上的所述经处理区域进行第一可靠性测试以产生第一结果; 基于第一可靠性测试的第一结果，通过改变材料，单元过程和过程序列中的至少一个来以组合的方式处理第二基板上的区域; 对所述第二基板上的所述经处理区域进行第二可靠性测试以产生第二结果; 以及基于所述第二结果来确定所述第一基板和所述第二基板是否满足预定质量阈值。

公开(公告)号：US08679988B2

公开(公告)日：2014-03-25

申请号：US13302777

申请日：2011-11-22

Applicant: Albert Lee ,  Chi-I Lang

Inventor： Albert Lee ,  Chi-I Lang

IPC: H01L21/00

CPC classification number: H01L45/1616 ,  H01L27/2409 ,  H01L45/08 ,  H01L45/146

Abstract: In some embodiments, the present invention discloses plasma processing at interfaces of an ALD metal oxide film with top and bottom electrodes to improve the ReRAM device characteristics. The interface processing can comprise an oxygen inhibitor step with a bottom polysilicon electrode to prevent oxidation of the polysilicon layer, enhancing the electrical contact of the metal oxide film with the polysilicon electrode. The interface processing can comprise an oxygen enrichment step with a top metal electrode to increase the resistivity of the metal oxide layer, providing an integrated current limiter layer.

Abstract translation: 在一些实施例中，本发明公开了在ALD金属氧化物膜与顶部和底部电极的界面处的等离子体处理，以改善ReRAM器件的特性。 界面处理可以包括具有底部多晶硅电极的氧抑制剂步骤，以防止多晶硅层氧化，增强金属氧化物膜与多晶硅电极的电接触。 界面处理可以包括具有顶部金属电极的富氧步骤以增加金属氧化物层的电阻率，从而提供集成的限流器层。

公开(公告)号：US08657966B2

公开(公告)日：2014-02-25

申请号：US13058803

申请日：2009-08-12

Applicant: Nikhil D. Kalyankar ,  Chi-I Lang ,  Zachary Fresco

Inventor： Nikhil D. Kalyankar ,  Chi-I Lang ,  Zachary Fresco

IPC: B08B3/00 ,  C11D7/00

CPC classification number: C11D11/0047 ,  B08B3/10 ,  C11D7/265 ,  C11D7/28 ,  C11D7/34 ,  C11D7/36 ,  C11D7/5004

Abstract: Embodiments of the current invention describe cleaning solutions to clean the surface of a photomask, methods of cleaning the photomask using at least one of the cleaning solutions, and combinatorial methods of formulating the cleaning solutions. The cleaning solutions are formulated to preserve the optical properties of the photomask, and in particular, of a phase-shifting photomask.

Abstract translation: 本发明的实施例描述了清洁光掩模表面的清洁溶液，使用至少一种清洁溶液清洁光掩模的方法以及配制清洁溶液的组合方法。 制备清洁溶液以保持光掩模的光学性质，特别是相移光掩模。

公开(公告)号：US08609475B2

公开(公告)日：2013-12-17

申请号：US13602637

申请日：2012-09-04

Applicant: Zhi-Wen Sun ,  Tony Chiang ,  Chi-I Lang ,  Jinhong Tong

Inventor： Zhi-Wen Sun ,  Tony Chiang ,  Chi-I Lang ,  Jinhong Tong

IPC: H01L21/20 ,  H01L21/00 ,  H01L21/16 ,  H01L21/8229

CPC classification number: H01L45/1253 ,  H01L45/04 ,  H01L45/1233 ,  H01L45/146 ,  H01L45/1608 ,  H01L45/1616

Abstract: Methods for forming a NiO film on a substrate for use with a resistive switching memory device are presenting including: preparing a nickel ion solution; receiving the substrate, where the substrate includes a bottom electrode, the bottom electrode utilized as a cathode; forming a Ni(OH)2 film on the substrate, where the forming the Ni(OH)2 occurs at the cathode; and annealing the Ni(OH)2 film to form the NiO film, where the NiO film forms a portion of a resistive switching memory element. In some embodiments, methods further include forming a top electrode on the NiO film and before the forming the Ni(OH)2 film, pre-treating the substrate. In some embodiments, methods are presented where the bottom electrode and the top electrode are a conductive material.

Abstract translation: 在电阻式切换存储装置使用的基板上形成NiO膜的方法包括：制备镍离子溶液; 接收衬底，其中衬底包括底部电极，用作阴极的底部电极; 在衬底上形成Ni（OH）2膜，其中在阴极处形成Ni（OH）2; 并且还原Ni（OH）2膜以形成NiO膜，其中NiO膜形成电阻式开关存储元件的一部分。 在一些实施例中，方法还包括在NiO膜上形成顶部电极，并且在形成Ni（OH）2膜之前，预处理衬底。 在一些实施例中，呈现了底部电极和顶部电极为导电材料的方法。

公开(公告)号：US08580697B1

公开(公告)日：2013-11-12

申请号：US13031077

申请日：2011-02-18

Applicant: Chi-I Lang ,  Judy H. Huang ,  Michael Barnes ,  Sunil Shanker

Inventor： Chi-I Lang ,  Judy H. Huang ,  Michael Barnes ,  Sunil Shanker

IPC: H01L21/02

CPC classification number: H01L21/76837 ,  H01L21/02164 ,  H01L21/02216 ,  H01L21/02271 ,  H01L21/0234 ,  H01L21/31612 ,  H01L21/76826

Abstract: The present invention meets these needs by providing improved methods of filling gaps. In certain embodiments, the methods involve placing a substrate into a reaction chamber and introducing a vapor phase silicon-containing compound and oxidant into the chamber. Reactor conditions are controlled so that the silicon-containing compound and the oxidant are made to react and condense onto the substrate. The chemical reaction causes the formation of a flowable film, in some instances containing Si—OH, Si—H and Si—O bonds. The flowable film fills gaps on the substrates. The flowable film is then converted into a silicon oxide film, for example by plasma or thermal annealing. The methods of this invention may be used to fill high aspect ratio gaps, including gaps having aspect ratios ranging from 3:1 to 10:1.

公开(公告)号：US08551560B2

公开(公告)日：2013-10-08

申请号：US12471310

申请日：2009-05-22

Applicant: Jinhong Tong ,  Zhi-Wen Sun ,  Chi-I Lang ,  Nitin Kumar ,  Bob Kong ,  Zachary Fresco

Inventor： Jinhong Tong ,  Zhi-Wen Sun ,  Chi-I Lang ,  Nitin Kumar ,  Bob Kong ,  Zachary Fresco

IPC: C23C18/18 ,  C23C18/34 ,  C23C18/36 ,  C23C18/50

CPC classification number: H01L21/288 ,  C23C18/1605 ,  C23C18/168 ,  C23C18/50 ,  H01L21/0332 ,  H01L21/3105 ,  H01L21/76829 ,  H01L21/76849

Abstract: Methods for improving selective deposition of a capping layer on a patterned substrate are presented, the method including: receiving the patterned substrate, the patterned substrate including a conductive region and a dielectric region; forming a molecular masking layer (MML) on the dielectric region; preparing an electroless (ELESS) plating bath, where the ELESS plating bath includes: a cobalt (Co) ion source: a complexing agent: a buffer: a tungsten (W) ion source: and a reducing agent; and reacting the patterned substrate with the ELESS plating bath for an ELESS period at an ELESS temperature and an ELESS pH so that the capping layer is selectively formed on the conductive region. In some embodiments, methods further include a pH adjuster for adjusting the ELESS pH to a range of approximately 9.0 pH to 9.2 pH. In some embodiments, the pH adjuster is tetramethylammonium hydroxide (TMAH). In some embodiments, the MML is hydrophilic.

Abstract translation: 提出了用于改善在图案化衬底上的覆盖层的选择性沉积的方法，所述方法包括：接收图案化衬底，所述图案化衬底包括导电区域和电介质区域; 在介电区上形成分子屏蔽层（MML）; 制备无电镀（ELESS）电镀浴，其中ELESS电镀浴包括：钴（Co）离子源：络合剂：缓冲剂：钨（W）离子源和还原剂; 并在ELESS温度和ELESS pH下使图案化衬底与ELESS电镀浴反应ELESS周期，从而在导电区域上选择性地形成覆盖层。 在一些实施方案中，方法还包括用于将ELESS pH调节至约9.0 pH至9.2 pH范围的pH调节剂。 在一些实施方案中，pH调节剂是氢氧化四甲基铵（TMAH）。 在一些实施方案中，MML是亲水的。