利索-全球专利检索

  1. 登录
  2. 注册

搜索结果

157 条记录 (耗时 0.023 秒)

    Bi-layer hard mask for the patterning and etching of nanometer size MRAM devices
    61.
    发明申请
    Bi-layer hard mask for the patterning and etching of nanometer size MRAM devices 有权
    用于纳米尺寸MRAM器件的图案化和蚀刻的双层硬掩模

    公开(公告)号：US20120028373A1

    公开(公告)日：2012-02-02

    申请号：US12804840

    申请日：2010-07-30

    申请人： Rodolfo Belen ,  Rongfu Xiao ,  Tom Zhong ,  Witold Kula ,  Chyu-Jiuh Torng

    发明人： Rodolfo Belen ,  Rongfu Xiao ,  Tom Zhong ,  Witold Kula ,  Chyu-Jiuh Torng

    IPC分类号： H01L43/12 ,  B32B5/00 ,  B32B7/02 ,  B32B15/04

    CPC分类号： H01L43/12 ,  Y10T428/12535 ,  Y10T428/24975 ,  Y10T428/266 ,  Y10T428/31504 ,  Y10T428/31678

    摘要： A composite hard mask is disclosed that prevents build up of metal etch residue in a MRAM device during etch processes that define an MTJ shape. As a result, MTJ shape integrity is substantially improved. The hard mask has a lower non-magnetic spacer, a middle conductive layer, and an upper sacrificial dielectric layer. The non-magnetic spacer serves as an etch stop during a pattern transfer with fluorocarbon plasma through the conductive layer. A photoresist pattern is transferred through the dielectric layer with a first fluorocarbon etch. Then the photoresist is removed and a second fluorocarbon etch transfers the pattern through the conductive layer. The dielectric layer protects the top surface of the conductive layer during the second fluorocarbon etch and during a substantial portion of a third RIE step with a gas comprised of C, H, and O that transfers the pattern through the underlying MTJ layers.

    摘要翻译： 公开了一种复合硬掩模，其防止在限定MTJ形状的蚀刻工艺期间在MRAM器件中积累金属蚀刻残留物。 结果，MTJ形状完整性得到显着提高。 硬掩模具有较低的非磁性间隔物，中间导电层和上部牺牲介电层。 在通过导电层的氟碳等离子体的图案转印期间，非磁性间隔物用作蚀刻停止层。 光致抗蚀剂图案通过第一氟碳蚀刻转移通过电介质层。 然后去除光致抗蚀剂，并且第二氟碳蚀刻将图案转移通过导电层。 介电层在第二次氟碳蚀刻期间保护导电层的顶表面，并在第三次RIE步骤的大部分期间保护由C，H和O组成的气体，以将图案转移通过下面的MTJ层。

    FCC-like trilayer AP2 structure for CPP GMR EM improvement
    63.
    发明授权
    FCC-like trilayer AP2 structure for CPP GMR EM improvement 有权
    FCC类三层AP2结构，用于CPP GMR EM改进

    公开(公告)号：US08012316B2

    公开(公告)日：2011-09-06

    申请号：US12583742

    申请日：2009-08-25

    申请人： Kunliang Zhang ,  Dan Abels ,  Min Li ,  Chyu-Jiuh Torng ,  Chen-Jung Chien ,  Yu-Hsia Chen

    发明人： Kunliang Zhang ,  Dan Abels ,  Min Li ,  Chyu-Jiuh Torng ,  Chen-Jung Chien ,  Yu-Hsia Chen

    IPC分类号： C23C14/14

    CPC分类号： H01L43/10 ,  B82Y10/00 ,  B82Y25/00 ,  B82Y40/00 ,  G11B5/3906 ,  H01F10/16 ,  H01F10/3236 ,  H01F10/3259 ,  H01F10/3272 ,  H01F41/302

    摘要： A method of forming a CPP-GMR spin valve having a pinned layer with an AP2/coupling/AP1 configuration is disclosed wherein the AP2 portion is a FCC-like trilayer having a composition represented by CoZFe(100-Z)/Fe(100-X)TaX/CoZFe(100-Z) or CoZFe(100-Z)/FeYCo(100-Y)/CoZFe(100-Z) where x is 3 to 30 atomic %, y is 40 to 100 atomic %, and z is 75 to 100 atomic %. Preferably, z is 90 to provide a face centered cubic structure that minimizes electromigration. Optionally, the middle layer is comprised of an Fe rich alloy such as FeCr, FeV, FeW, FeZr, FeNb, FeHf, or FeMo. EM performance is improved significantly compared to a spin valve with a conventional AP2 Co50Fe50 or Co75Fe25 single layer. MR ratio is also increased and RA is maintained at an acceptable level. The coupling layer is preferably Ru and the AP1 layer may be comprised of a lamination of CoFe and Cu layers as in [CoFe/Cu]2/CoFe.

    摘要翻译： 公开了一种形成具有AP2 /偶联/ AP1构型的钉扎层的CPP-GMR自旋阀的方法，其中AP2部分是具有由CoZFe（100-Z）/ Fe（100-Z）/ Fe X）TaX / CoZFe（100-Z）或CoZFe（100-Z）/ FeYCo（100-Y）/ CoZFe（100-Z），其中x为3至30原子％，y为40至100原子％ 为75〜100原子％。 优选地，z为90以提供使电迁移最小化的面心立方结构。 任选地，中间层由富Fe合金如FeCr，FeV，FeW，FeZr，FeNb，FeHf或FeMo组成。 与具有常规AP2 Co50Fe50或Co75Fe25单层的自旋阀相比，EM性能显着提高。 MR比也增加，RA维持在可接受的水平。 耦合层优选为Ru，并且AP1层可以由如[CoFe / Cu] 2 / CoFe中的CoFe和Cu层的层叠构成。

    High density spin-transfer torque MRAM process
    65.
    发明申请
    High density spin-transfer torque MRAM process 有权

    公开(公告)号：US20110101478A1

    公开(公告)日：2011-05-05

    申请号：US12930333

    申请日：2011-01-04

    申请人： Tom Zhong ,  Chyu-Jiuh Torng ,  Rongfu Xiao ,  Adam Zhong ,  Wai-Ming Johnson Kan ,  Daniel Liu

    发明人： Tom Zhong ,  Chyu-Jiuh Torng ,  Rongfu Xiao ,  Adam Zhong ,  Wai-Ming Johnson Kan ,  Daniel Liu

    IPC分类号： H01L29/82

    CPC分类号： H01L27/228 ,  H01L43/12

    摘要： A STT-MRAM integration scheme is disclosed wherein the connection between a MTJ and CMOS metal is simplified by forming an intermediate via contact (VAC) on a CMOS landing pad, a metal (VAM) pad that contacts and covers the VAC, and a MTJ on the VAM. A dual damascene process is performed to connect BIT line metal to CMOS landing pads through VAC/VAM/MTJ stacks in a device region, and to connect BIT line connection pads to CMOS connection pads through BIT connection vias outside the device region. The VAM pad is a single layer or composite made of Ta, TaN, or other conductors which serves as a diffusion barrier, has a highly smooth surface for MTJ formation, and provides excellent selectivity with refill dielectric materials during a chemical mechanical polish process. Each VAC is from 500 to 3000 Angstroms thick to minimize additional circuit resistance and minimize etch burden.

    Method of high density memory fabrication
    66.
    发明申请
    Method of high density memory fabrication 有权
    高密度存储器制造方法

    公开(公告)号：US20110073917A1

    公开(公告)日：2011-03-31

    申请号：US12586900

    申请日：2009-09-29

    申请人： Tom Zhong ,  Adam Zhong ,  Wai-Ming J. Kan ,  Chyu-Jiuh Torng

    发明人： Tom Zhong ,  Adam Zhong ,  Wai-Ming J. Kan ,  Chyu-Jiuh Torng

    IPC分类号： H01L29/66 ,  H01L21/4763

    CPC分类号： H01L27/105 ,  H01L21/76819 ,  H01L21/7684 ,  H01L23/522 ,  H01L27/228 ,  H01L2924/0002 ,  H01L2924/00

    摘要： The structure and method of formation of an integrated CMOS level and active device level that can be a memory device level. The integration includes the formation of a “super-flat” interface between the two levels formed by the patterning of a full complement of active and dummy interconnecting vias using two separate patterning and etch processes. The active vias connect memory devices in the upper device level to connecting pads in the lower CMOS level. The dummy vias may extend up to an etch stop layer formed over the CMOS layer or may be stopped at an intermediate etch stop layer formed within the device level. The dummy vias thereby contact memory devices but do not connect them to active elements in the CMOS level.

    摘要翻译： 集成CMOS级别和有源器件级别的结构和方法可以是存储器件级。 整合包括通过使用两个单独的图案化和蚀刻工艺对完整的有源和虚拟互连通孔进行图案化形成的两层之间形成“超平面”界面。 有源通孔将上部器件电平的存储器件连接到较低CMOS电平的连接焊盘。 虚拟通孔可以延伸到在CMOS层上形成的蚀刻停止层，或者可以在形成在器件级内的中间蚀刻停止层处停止。 因此，虚拟通孔接触存储器件，但不将它们连接到CMOS电平中的有源元件。

    Method of double patterning and etching magnetic tunnel junction structures for spin-transfer torque MRAM devices
    67.
    发明授权
    Method of double patterning and etching magnetic tunnel junction structures for spin-transfer torque MRAM devices 有权
    双重图案化和蚀刻用于自旋转移转矩MRAM器件的磁性隧道结结构的方法

    公开(公告)号：US07863060B2

    公开(公告)日：2011-01-04

    申请号：US12383298

    申请日：2009-03-23

    申请人： Rodolfo Belen ,  Tom Zhong ,  Witold Kula ,  Chyu-Jiuh Torng

    发明人： Rodolfo Belen ,  Tom Zhong ,  Witold Kula ,  Chyu-Jiuh Torng

    IPC分类号： H01L21/00

    CPC分类号： H01L27/228 ,  H01L43/12

    摘要： A method for forming a MTJ in a STT-MRAM is disclosed in which the easy-axis CD is determined independently of the hard-axis CD. One approach involves two photolithography steps each followed by two plasma etch steps to form a post in a hard mask which is transferred through a MTJ stack of layers. The hard mask has an upper Ta layer with a thickness of 300 to 400 Angstroms and a lower NiCr layer less than 50 Angstroms thick. The upper Ta layer is etched with a fluorocarbon etch while lower NiCr layer and underlying MTJ layers are etched with a CH3OH. Preferably, a photoresist mask layer is removed by oxygen plasma between the fluorocarbon and CH3OH plasma etches. A lower hard mask layer made of NiCr or the like is inserted to prevent formation and buildup of Ta etch residues that can cause device shunting.

    摘要翻译： 公开了一种用于在STT-MRAM中形成MTJ的方法，其中容易轴CD独立于硬轴CD来确定。 一种方法涉及两个光刻步骤，每个步骤分别采用两个等离子体蚀刻步骤，以在通过MTJ堆叠层传送的硬掩模中形成柱。 硬掩模具有厚度为300至400埃的上层Ta层和小于50埃厚的较低NiCr层。 用氟碳蚀刻蚀刻上层Ta层，同时用CH3OH蚀刻下层NiCr层和下层MTJ层。 优选地，在碳氟化合物和CH 3 OH等离子蚀刻之间的氧等离子体去除光致抗蚀剂掩模层。 插入由NiCr等制成的下部硬掩模层以防止可能导致器件分流的Ta蚀刻残留物的形成和积累。

    High performance MTJ element for STT-RAM and method for making the same
    68.
    发明授权
    High performance MTJ element for STT-RAM and method for making the same 有权
    用于STT-RAM的高性能MTJ元件和制作相同的方法

    公开(公告)号：US07750421B2

    公开(公告)日：2010-07-06

    申请号：US11880583

    申请日：2007-07-23

    申请人： Cheng T. Horng ,  Ru-Ying Tong ,  Chyu-Jiuh Torng ,  Witold Kula

    发明人： Cheng T. Horng ,  Ru-Ying Tong ,  Chyu-Jiuh Torng ,  Witold Kula

    IPC分类号： H01L29/82

    CPC分类号： H01L43/08 ,  B82Y25/00 ,  B82Y40/00 ,  G11C11/161 ,  H01F10/3272 ,  H01F10/329 ,  H01F10/3295 ,  H01F41/307 ,  H01L43/10 ,  H01L43/12

    摘要： A STT-MTJ MRAM cell that utilizes transfer of spin angular momentum as a mechanism for changing the magnetic moment direction of a free layer includes an IrMn pinning layer, a SyAP pinned layer, a naturally oxidized, crystalline MgO tunneling barrier layer that is formed on an Ar-ion plasma smoothed surface of the pinned layer and, in one embodiment, a free layer that comprises an amorphous layer of Co60Fe20B20 of approximately 20 angstroms thickness formed between two crystalline layers of Fe of 3 and 6 angstroms thickness respectively or on a single such layer. The free layer is characterized by a low Gilbert damping factor and by very strong polarizing action on conduction electrons. The resulting cell has a low critical current, a high dR/R and a plurality of such cells will exhibit a low variation of both resistance and pinned layer magnetization angular dispersion.

    摘要翻译： 利用自旋角度动量的转移作为改变自由层的磁矩方向的机构的STT-MTJ MRAM单元包括IrMn钉扎层，SyAP钉扎层，自然氧化的结晶的MgO隧穿势垒层，其形成于 钉扎层的Ar离子等离子体平滑表面，并且在一个实施例中，自由层包括分别在3和6埃厚度的Fe的两个结晶层之间形成的约20埃厚度的Co60Fe20B20的非晶层，或者在单个 这样的层。 自由层的特征在于低吉尔伯特阻尼因子和对传导电子的非常强的偏振作用。 所得到的电池具有低临界电流，高dR / R，并且多个这样的电池将呈现电阻和钉扎层磁化角分散的低变化。

    Hard bias design for extra high density recording
    70.
    发明授权
    Hard bias design for extra high density recording 有权
    用于超高密度记录的硬偏置设计

    公开(公告)号：US07688555B2

    公开(公告)日：2010-03-30

    申请号：US10868716

    申请日：2004-06-15

    申请人： Kunliang Zhang ,  Yun-Fei Li ,  Chyu-Jiuh Torng ,  Chen-Jung Chien

    发明人： Kunliang Zhang ,  Yun-Fei Li ,  Chyu-Jiuh Torng ,  Chen-Jung Chien

    IPC分类号： G11B5/39 ,  G11B5/127

    CPC分类号： B82Y25/00 ,  B82Y10/00 ,  G11B5/3912 ,  G11B5/3932 ,  G11B2005/3996

    摘要： A hard bias structure for biasing a free layer in a MR element within a read head is comprised of a composite hard bias layer having a Co78.6Cr5.2Pt16.2/Co65Cr15Pt20 configuration. The upper Co65Cr15Pt20 layer has a larger Hc value and a thickness about 2 to 10 times greater than that of the Co78.6Cr5.2Pt16.2 layer. The hard bias structure may also include a BCC underlayer such as FeCoMo which enhances the magnetic moment of the hard bias structure. Optionally, the thickness of the Co78.6Cr5.2Pt16.2 layer is zero and the Co65Cr15Pt20 layer is formed on the BCC underlayer. The present invention also encompasses a laminated hard bias structure. The Mrt value for the hard bias structure may be optimized by adjusting the thicknesses of the BCC underlayer and CoCrPt layers. As a result, a larger process window is realized and lower asymmetry output during a read operation is achieved.

    摘要翻译： 用于偏置读取头内的MR元件中的自由层的硬偏置结构由具有Co78.6Cr5.2Pt16.2 / Co65Cr15Pt20配置的复合硬偏置层组成。 Co65Cr15Pt20上层具有较大的Hc值，厚度约为Co78.6Cr5.2Pt16.2层的2〜10倍。 硬偏压结构还可以包括诸如FeCoMo的BCC底层，其增强了硬偏压结构的磁矩。 可选地，Co78.6Cr5.2Pt16.2层的厚度为零，Co65Cr15Pt20层形成在BCC底层上。 本发明还包括层压硬偏置结构。 可以通过调整BCC底层和CoCrPt层的厚度来优化硬偏置结构的Mrt值。 结果，实现了更大的处理窗口，并且在读取操作期间实现了较低的不对称输出。