公开(公告)号：US20240275282A1

公开(公告)日：2024-08-15

申请号：US18166576

申请日：2023-02-09

Applicant: GlobalFoundries U.S. Inc.

Inventor： Dzung T. TRAN ,  Shivraj G. Dharne ,  Asif Iqbal

IPC: H02M3/158 ,  H02M1/00 ,  H02M1/096 ,  H02M1/36

CPC classification number: H02M3/158 ,  H02M1/0009 ,  H02M1/096 ,  H02M1/36

Abstract: A reference circuit for an electronic device having a plurality of power supply voltages comprises a supply start-up circuit, a power-down start-up circuit, and a reference generating circuit. The supply start-up circuit comprising a resistive-capacitive (RC) circuit coupled between a first power supply voltage and a ground. The RC circuit includes a pulse node coupled between a first capacitor and a resistive element, and generates a power-up pulse signal at the pulse node. The power-down start-up circuit is powered by a second power supply voltage and comprises a pulse generation circuit that generates a first start-up signal. The reference generating circuit outputs a reference signal. The reference generating circuit exists a low-power mode when either of the power-up pulse signal and the first start-up signal is generated.

公开(公告)号：US20240274712A1

公开(公告)日：2024-08-15

申请号：US18109126

申请日：2023-02-13

Applicant: GlobalFoundries U.S. Inc.

Inventor： Francois Hebert

IPC: H01L29/78 ,  H01L29/16 ,  H01L29/66

CPC classification number: H01L29/7813 ,  H01L29/1608 ,  H01L29/66734

Abstract: Structures for a field-effect transistor and methods of forming a structure for a field-effect transistor. The structure comprises a semiconductor substrate including a first doped region, a second doped region, a third doped region, and a trench that includes a trench bottom, a first sidewall, and a second sidewall opposite to the first sidewall. The first doped region is disposed adjacent to the first sidewall of the trench, the second doped region is disposed adjacent to the second sidewall of the trench, the third doped region is disposed adjacent to the trench bottom of the trench. The third doped region connects the first doped region to the second doped region, and the first doped region, the second doped region, and the third doped region have a conductivity type. The structure further comprises a gate structure in the trench.

公开(公告)号：US20240274161A1

公开(公告)日：2024-08-15

申请号：US18166544

申请日：2023-02-09

Applicant: GlobalFoundries U.S. Inc.

Inventor： Dzung T. Tran ,  Navneet K. Jain

IPC: G11C5/14 ,  G01R19/165

CPC classification number: G11C5/147 ,  G01R19/16519

Abstract: Embodiments of the disclosure provide a structure and method to ground a reference voltage generator based on a detected supply voltage. A circuit structure according to the disclosure includes a pass gate. The pass gate includes a pair of transistors each coupled to an input signal. One of the pair of transistors of the pass gate includes a gate coupled to a static reference voltage. An inverter couples an output from the pass gate to a device node. The inverter includes a drain terminal, a gate terminal, and a back-gate terminal coupled to ground.

公开(公告)号：US20240266422A1

公开(公告)日：2024-08-08

申请号：US18166041

申请日：2023-02-08

Applicant: GlobalFoundries U.S. Inc.

Inventor： Anupam Dutta ,  Satyasuresh Vvss Choppalli ,  Rajendran Krishnasamy ,  Robert J. Gauthier, JR. ,  Anindya Nath

IPC: H01L29/745

CPC classification number: H01L29/7455

Abstract: Disclosed structures include a semiconductor controlled rectifier or bi-directional semiconductor controlled rectifier with a trigger voltage (Vtrig) that is tunable. Some structures include a semiconductor controlled rectifier with an Nwell and Pwell in a semiconductor layer, with a P-type diffusion region in the Nwell, and with an N-type diffusion region in the Pwell. Gate(s) on the well(s) are separated from the junction between the wells and from the diffusion regions. Other structures include a bidirectional semiconductor controlled rectifier with a Pwell between first and second Nwells in a semiconductor layer, with first P-type and N-type diffusion regions in the first Nwell, and with second P-type and N-type diffusion regions in the second Nwell. Gate(s) on the well(s) are separated from junctions between the Nwells and the Pwell and from any diffusion regions. In these structures, the gate(s) can be left floating or biased to tune Vtrig using gate leakage current.

公开(公告)号：US20240264374A1

公开(公告)日：2024-08-08

申请号：US18105304

申请日：2023-02-03

Applicant: GlobalFoundries U.S. Inc.

Inventor： Zhuojie Wu

IPC: G02B6/122 ,  G02B6/136 ,  H01L23/38 ,  H01L23/48

CPC classification number: G02B6/1228 ,  G02B6/136 ,  H01L23/38 ,  H01L23/481 ,  G02B2006/12121

Abstract: Structures for a cavity-mounted chip and methods of fabricating a structure for a cavity-mounted chip. The structure comprises a substrate including a cavity, a thermoelectric device inside the cavity, and a chip disposed inside the cavity adjacent to the thermoelectric device. The thermoelectric device includes a first plurality of pillars and a second plurality of pillars that alternate with the first plurality of pillars in a series circuit, the first plurality of pillars comprising an n-type semiconductor material, and the second plurality of pillars comprising a p-type semiconductor material.

公开(公告)号：US12046651B2

公开(公告)日：2024-07-23

申请号：US17515914

申请日：2021-11-01

Applicant: GLOBALFOUNDRIES U.S. Inc.

Inventor： James P. Mazza ,  Elizabeth Strehlow ,  Motoi Ichihashi ,  Xuelian Zhu ,  Jia Zeng

IPC: H01L27/02 ,  H01L23/528 ,  H01L29/423

CPC classification number: H01L29/42376 ,  H01L23/5286

Abstract: The present disclosure relates to semiconductor structures and, more particularly, to a logic cell layout design for high density transistors and methods of manufacture. The structure includes a plurality of active gates in a high density transistor, and at least one dummy gate which is continuous and is adjacent to at least one active gate of the active gates in a multi-row cell of the high density transistor.

公开(公告)号：US12046633B2

公开(公告)日：2024-07-23

申请号：US17157269

申请日：2021-01-25

Applicant: GLOBALFOUNDRIES U.S. Inc.

Inventor： Mark D. Levy ,  Siva P. Adusumilli ,  Johnatan A. Kantarovsky ,  Vibhor Jain

IPC: H01L29/06 ,  H01L21/308 ,  H01L21/764 ,  H01L27/06 ,  H01L27/07 ,  H01L29/08

CPC classification number: H01L29/0657 ,  H01L21/308 ,  H01L21/764 ,  H01L27/0635 ,  H01L27/0755 ,  H01L29/0653 ,  H01L29/0821

Abstract: The present disclosure relates to semiconductor structures and, more particularly, to airgap structures in a doped region under one or more transistors and methods of manufacture. The structure includes: a semiconductor material comprising a doped region; one or more sealed airgap structures breaking up the doped region of the semiconductor material; and a field effect transistor over the one or more sealed airgap structures and the semiconductor material.

公开(公告)号：US20240243175A1

公开(公告)日：2024-07-18

申请号：US18098188

申请日：2023-01-18

Applicant: GlobalFoundries U.S. Inc.

Inventor： Venkata Narayana Rao Vanukuru ,  Steven M. Shank

IPC: H01L29/10 ,  H01L21/74 ,  H01L27/12

CPC classification number: H01L29/1087 ,  H01L21/743 ,  H01L27/1203

Abstract: Structures including a field-effect transistor field-effect and methods of forming a structure including a field-effect transistor. The structure comprises a trench isolation region in a substrate, and a body contact region that extends through the trench isolation region to the substrate. The structure further comprises a field-effect transistor including a gate connector, a first gate finger that extends from the gate connector, a second gate finger that extends from the gate connector, and a source/drain region disposed between the first gate finger and the second gate finger. The gate connector is positioned over the trench isolation region. The structure further comprises a gate contact coupled to the gate connector, and a body contact that penetrates through a portion of the gate connector to the body contact region.

公开(公告)号：US12040388B2

公开(公告)日：2024-07-16

申请号：US17525634

申请日：2021-11-12

Applicant: GLOBALFOUNDRIES U.S. Inc.

Inventor： Hong Yu ,  Judson R. Holt ,  Alexander Derrickson

IPC: H01L29/735 ,  H01L29/08 ,  H01L29/10 ,  H01L29/165 ,  H01L29/66

CPC classification number: H01L29/735 ,  H01L29/0808 ,  H01L29/0821 ,  H01L29/1008 ,  H01L29/165 ,  H01L29/6625

Abstract: The present disclosure relates to semiconductor structures and, more particularly, to a lateral bipolar transistor and methods of manufacture. The structure includes: an extrinsic base having at least one sidewall with a gradient concentration of semiconductor material; an emitter on a first side of the extrinsic base; and a collector on a second side of the extrinsic base.

公开(公告)号：US20240234498A9

公开(公告)日：2024-07-11

申请号：US17969768

申请日：2022-10-20

Applicant: GlobalFoundries Singapore Pte. Ltd.

Inventor： Xinshu Cai ,  Shyue Seng Tan ,  Vibhor Jain ,  John J. Pekarik

IPC: H01L29/06 ,  H01L29/08 ,  H01L29/78

CPC classification number: H01L29/0653 ,  H01L29/0847 ,  H01L29/7825

Abstract: Structures for a junction field-effect transistor and methods of forming a structure for a junction field-effect transistor. The structure comprises a first gate on a top surface of a semiconductor substrate, a second gate beneath the top surface of the semiconductor substrate, and a channel region in the semiconductor substrate. The first gate is positioned between a source and a drain, and the channel region positioned between the first gate and the second gate.