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    Forward and backward propagation methods and structures for coherent optical receiver
    61.
    发明授权
    Forward and backward propagation methods and structures for coherent optical receiver 有权

    公开(公告)号：US10128958B1

    公开(公告)日：2018-11-13

    申请号：US15792597

    申请日：2017-10-24

    Applicant: INPHI CORPORATION

    Inventor： Damián A. Morero ,  Mario R. Hueda ,  Oscar E. Agazzi

    IPC: H04B10/079 ,  H04B10/61 ,  H04L1/00

    Abstract: A method and structure for signal propagation in a coherent optical receiver device. Asynchronous equalization helps to reduce complexity and power dissipation, and also improves the robustness of timing recovery. However, conventional devices using inverse interpolation filters ignore adaptation algorithms. The present invention provides for forward propagation and backward propagation. In the forward case, the filter input signal is forward propagated through a filter to the adaptation engine, while, in the backward case, the error signal is backward propagated through a filter to the asynchronous domain. Using such forward and backward propagation schemes reduces implementation complexity while providing optical device performance.

    MACH-ZEHNDER MODULATOR DRIVER
    62.
    发明申请
    MACH-ZEHNDER MODULATOR DRIVER 审中-公开

    公开(公告)号：US20180321520A1

    公开(公告)日：2018-11-08

    申请号：US16032947

    申请日：2018-07-11

    Applicant: INPHI CORPORATION

    Inventor： Abdellatif EL-MOZNINE ,  Bruno TOURETTE ,  Hessam MOHAJERI

    IPC: G02F1/025 ,  G02F1/225 ,  G02F1/01 ,  H03G3/20 ,  H04B10/54 ,  G02F1/21

    CPC classification number: G02F1/025 ,  G02F1/0121 ,  G02F1/2255 ,  G02F1/2257 ,  G02F2001/212 ,  G02F2201/12 ,  H03G3/20 ,  H04B10/54

    Abstract: A driver configuration for driving a Mach-Zehnder modulator (MZM) includes a first driver supplied by a first voltage and a second voltage and configured to provide a first two complimentary outputs respectively to a first N-electrode of a first branch of the MZM and a second N-electrode of a second branch of the MZM. Additionally, the driver configuration includes a second driver supplied by a third voltage and a fourth voltage and configured to provide a second two complimentary outputs respectively to a first P-electrode of the first branch and a second P-electrode of the second branch. The driver configuration sets a difference between the third voltage and the fourth voltage equal to a difference between the first voltage and the second voltage to provide a same peak-to-peak differential swing for modulating light wave through each transmission line and output a modulated light with twice of the peak-to-peak differential swing.

    CMOS externally modulated laser driver
    67.
    发明授权
    CMOS externally modulated laser driver 有权

    公开(公告)号：US10096964B1

    公开(公告)日：2018-10-09

    申请号：US15605829

    申请日：2017-05-25

    Applicant: INPHI CORPORATION

    Inventor： Karim Abdelhalim ,  Jorge Pernillo ,  Halil Cirit ,  Michael Le

    IPC: H01S3/09 ,  H03M1/08 ,  H01S3/0933 ,  H01S3/091 ,  H01S5/042

    Abstract: The present invention relates to telecommunication techniques and integrated circuit (IC) devices. In a specific embodiment, the present invention provides a laser deriver apparatus that includes a main DAC section and a mini DAC section. The main DAC section processes input signal received from a pre-driver array and generates an intermediate output signal. The mini DAC section provides a compensation signal to reduce distortion of the intermediate output signal. The intermediate output signal is coupled to output terminals through a cascode section and/or a T-coil section. There are other embodiments as well.

    SR latch circuit with single gate delay
    68.
    发明授权
    SR latch circuit with single gate delay 有权

    公开(公告)号：US10056883B2

    公开(公告)日：2018-08-21

    申请号：US15451196

    申请日：2017-03-06

    Applicant: INPHI CORPORATION

    Inventor： Travis William Lovitt

    IPC: H03H7/30 ,  H03H7/40 ,  H03K5/159 ,  H03K3/012 ,  H03K3/356 ,  H03M9/00

    CPC classification number: H03K3/012 ,  H03K3/356104 ,  H03K3/356113 ,  H03M9/00 ,  H04B1/40 ,  H04L25/03057 ,  H04L25/03146

    Abstract: An SR latch circuit with single gate delay is provided. The circuit has an enable input and an SR latch. There is first input stage having an input for receiving a set input and having an output for producing a first component of the SR latch circuit output, the first input stage having only one transistor that receives the enable input, the first input stage becoming transparent while enabled, the first input stage having a single gate delay between the input of the first input stage and the output of the first input stage. There is a second input stage having an input for receiving a reset input and having an output for producing a second component of the SR latch circuit output, the second input stage having only one transistor that receives the enable input, the second input stage becoming transparent while enabled, the second input stage having a single gate delay between the input of the second input stage and the output of the second input stage.

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