公开(公告)号：US11715757B2

公开(公告)日：2023-08-01

申请号：US18074617

申请日：2022-12-05

Applicant: Microchip Technology Incorporated

Inventor： Yaojian Leng ,  Justin Sato

IPC: H01L23/522 ,  H01L23/52 ,  H01L23/528 ,  H01L49/02

CPC classification number: H01L28/91 ,  H01L23/5223

Abstract: A three-dimensional metal-insulator-metal (MIM) capacitor is formed in an integrated circuit structure. The 3D MIM capacitor may include a bottom conductor including a bottom plate portion (e.g., formed in a metal interconnect layer) and vertically-extending sidewall portions extending from the bottom plate portion. An insulator layer is formed on the bottom plate portion and the vertically extending sidewall portions of the bottom conductor. A top conductor is formed over the insulating layer, such that the top conductor is capacitively coupled to both the bottom plate portion and the vertically extending sidewall portions of the bottom conductor, to thereby define an increased area of capacitive coupling between the top and bottom conductors. The vertically extending sidewall portions of the bottom conductor may be formed in a single metal layer or by components of multiple metal layers.

公开(公告)号：US20230231938A1

公开(公告)日：2023-07-20

申请号：US18125857

申请日：2023-03-24

Applicant: Microchip Technology Incorporated

Inventor： William Mahany ,  Ian Saturley ,  Lakshmi Narasimhan ,  Riyas Kattukandan ,  Ramya Kuppusamy ,  Robert Zakowicz

IPC: H04L69/22 ,  G06F9/4401 ,  H04J3/06 ,  H04L12/10

CPC classification number: H04L69/22 ,  G06F9/4418 ,  H04J3/0658 ,  H04L12/10

Abstract: An EtherCAT device is disclosed. The EtherCAT device comprises a data input port to receive a signal representing data, the signal representing one of a plurality of possible logical values; and a degradation calculation circuit. The degradation calculation circuit is to read, demodulate, and convert the received signal into a digital domain representation; process the digital domain representation into slices, where the value of the received signal at a respective time is represented in a respective one of the slices; determine differences between the respective slices and reference slices; identify an intended logical value of the received signal responsive to the determined differences; determine a quantification of error at the respective time responsive to the identified logical value and the determined differences; and determine a signal quality index responsive to the determined quantification of error.

公开(公告)号：US11700146B2

公开(公告)日：2023-07-11

申请号：US17409858

申请日：2021-08-24

Applicant: Microchip Technology Incorporated

Inventor： Galin I. Ivanov

IPC: H04L12/413

CPC classification number: H04L12/413

Abstract: An apparatus may be communicatively coupled to other nodes in a network. The apparatus may include a control circuit configured to repeatedly issue transmission cycles to the other nodes. A given transmission cycle may include a least one send slot for each of the other nodes to send data. The control circuit may be configured to initiate transmission cycles by issuing beacon signals to the other nodes. The control circuit may be configured to determine when to issue a beacon signal in a given transmission cycle by determining that all of the other nodes have completed all associated send slots in an immediately previous transmission cycle and based upon a determination of the completion of the other nodes' transmission, delaying transmission of the beacon signal for the given transmission cycle.

公开(公告)号：US11696406B2

公开(公告)日：2023-07-04

申请号：US17492354

申请日：2021-10-01

Applicant: Microchip Technology Incorporated

Inventor： Ajay Kumar

IPC: H05K1/16 ,  H05K3/22 ,  H01F38/14

CPC classification number: H05K1/162 ,  H01F38/14 ,  H05K1/165 ,  H05K3/225 ,  H01F2038/146 ,  H05K2201/10151

Abstract: Apparatus and methods of automatically trimming a PCB-based LC circuit. The apparatus may comprise an interface to a printed circuit board (PCB). The PCB may include a PCB inductor and a PCB capacitor to form an LC circuit. The LC circuit may have an LC circuit frequency. The apparatus may comprise a variable capacitor communicatively coupled to the interface and configured to adjust an effective capacitance of the LC circuit.

公开(公告)号：US20230179208A1

公开(公告)日：2023-06-08

申请号：US17823418

申请日：2022-08-30

Applicant: Microchip Technology Incorporated

Inventor： Waleed El-halwagy ,  William Roberts ,  Mehran Aliahmad

IPC: H03L7/099 ,  H03L7/091

CPC classification number: H03L7/0992 ,  H03L7/091

Abstract: One or more examples relate to an apparatus includes an error detector, an oscillator, an analog proportional path, and a digital integral path. The oscillator includes an analog proportional input, a digital integral input, and an analog integral input. The analog proportional path to provide a control signal for the analog proportional input of the oscillator. The digital integral path to provide a control for the digital integral input and the analog integral input of the oscillator. A first signal path of an interface includes a direct coupling between the digital phase detector and integrator and the digital integral input of the oscillator. A second signal path of the interface includes a digital-to-analog converter (DAC) with a filtered delta-sigma modulator (DSM) input between the digital phase detector and integrator and the analog integral input of the oscillator.

公开(公告)号：US20230176937A1

公开(公告)日：2023-06-08

申请号：US18075458

申请日：2022-12-06

Applicant: Microchip Technology Incorporated

Inventor： Michael Catherwood ,  David Mickey

IPC: G06F11/07 ,  G06F9/30

CPC classification number: G06F11/0745 ,  G06F9/30101

Abstract: A computer system includes a non-transitory computer-readable memory to store (a) a vector table including an exception vector pointing to an exception handler and (b) a vector fail address of a vector fetch bus error handler, and a processor to identify an exception, initiate an exception vector fetch in response to the identified exception to read the exception vector from the vector table, identify a vector fetch bus error associated with the exception vector fetch, access the vector fail address of the vector fetch bus error handler in response to the vector fetch bus error, and execute the vector fetch bus error handler.

公开(公告)号：US11663146B2

公开(公告)日：2023-05-30

申请号：US16806227

申请日：2020-03-02

Applicant: Microchip Technology Incorporated

Inventor： Michael Simmons

IPC: G06F12/14 ,  G06F3/06

CPC classification number: G06F12/1416 ,  G06F3/0616 ,  G06F3/0653 ,  G06F3/0659 ,  G06F3/0679

Abstract: An apparatus includes a database with device profiles, and a device programmer. The device programmer includes instructions. The instructions, when read and executed by a processor, cause the device programmer to identify a device identifier of an electronic device. The device programmer is further caused to, based upon the device identifier, access device data from the database. The device programmer is further caused to, based upon the device data, determine an area of memory of the electronic device that can be written. The device programmer is further caused to, based on the determination of the area of memory of the electronic device that can be written, write data to the area of memory.

公开(公告)号：US20230160836A1

公开(公告)日：2023-05-25

申请号：US18093032

申请日：2023-01-04

Applicant: Microchip Technology Incorporated

Inventor： Yaojian Leng

IPC: G01N21/95 ,  H01L23/532 ,  H01L23/528 ,  H01L23/522 ,  H01L31/103 ,  H01L21/66 ,  G01N21/47 ,  G01N21/88 ,  H01L31/02 ,  G01N17/02

CPC classification number: G01N21/9501 ,  H01L23/53238 ,  H01L23/528 ,  H01L23/5226 ,  H01L31/103 ,  H01L22/14 ,  G01N21/47 ,  G01N21/8851 ,  H01L31/02005 ,  G01N17/02 ,  G01N2201/06113 ,  G01N2021/4735

Abstract: Systems and methods for monitoring copper corrosion in an integrated circuit (IC) device are disclosed. A corrosion-sensitive structure formed in the IC device may include a p-type active region adjacent an n-type active region to define a p-n junction space charge region. A copper region formed over the silicon may be connected to both the p-region and n-region by respective contacts, to thereby define a short circuit. Light incident on the p-n junction space charge region, e.g., during a CMP process, creates a current flow through the metal region via the short circuit, which drives chemical reactions that cause corrosion in the copper region. Due to the short circuit configuration, the copper region is highly sensitive to corrosion. The corrosion-sensitive structure may be arranged with less corrosion-sensitive copper structures in the IC device, with the corrosion-sensitive structure used as a proxy to monitor for copper corrosion in the IC device.

公开(公告)号：US11658593B2

公开(公告)日：2023-05-23

申请号：US17731884

申请日：2022-04-28

Applicant: Microchip Technology Incorporated

Inventor： Keith Edwin Curtis

IPC: H02P8/00 ,  H02P8/14 ,  G05B19/416

CPC classification number: H02P8/14 ,  G05B19/416 ,  G05B2219/33088 ,  G05B2219/43139

Abstract: Automated speed ramp control of stepper motor acceleration and deceleration using direct memory access (DMA) and core independent peripherals (CIPs) comprises a numerically controlled oscillator (NCO) controlled through direct memory access (DMA) transfers of prescale values used in combination with a clock oscillator to generate clock pulses that are a function of the clock oscillator frequency and the prescale values. This automates changing the frequency of the NCO, thereby controlling steeper motor speed, without requiring computer processing unit (CPU) overhead. The DMA module is enabled during a first number of clock pulses for step speed acceleration, disabled during a second number of clock pulses for normal operation at full step speed, and then re-enabled during a third number of clock pulses for step speed deceleration. A table in memory may store and provide a plurality of acceleration and deceleration prescale values for DMA transfers to the NCO.

公开(公告)号：US20230135952A1

公开(公告)日：2023-05-04

申请号：US17744171

申请日：2022-05-13

Applicant: Microchip Technology Incorporated

Inventor： Kwok Kong ,  William Brent Wilson ,  Ihab Jaser ,  Donia Sebastian ,  Dan McLeran

IPC: G06F3/06

Abstract: A system (e.g., NVMe controller) for managing access to a memory resource by multiple users may include memory storing function queue categorizations for function queues associated with each user, and circuitry to store and execute a multi-user arbitration algorithm that arbitrates access to the memory resource by the multiple users. The function queue categorizations assign a function category to each function queue associated with each user. The multi-user arbitration algorithm includes (a) selecting an intra-user winning function queue for each respective user by performing an intra-user function queue arbitration of the function queues associated with the respective user based on the function queue categorizations associated with the arbitrated function queues, (b) selecting an inter-user winning function queue by performing an inter-user function queue arbitration of the intra-user winning function queues selected for the multiple users, and (c) serving a function from the inter-user winning function queue to the memory resource.