公开(公告)号：US20050275984A1

公开(公告)日：2005-12-15

申请号：US10866024

申请日：2004-06-14

Applicant: James Liu ,  Jimmy Hsieh ,  Sheng-Lyang Jang ,  Hsueh-Ming Lu

Inventor： James Liu ,  Jimmy Hsieh ,  Sheng-Lyang Jang ,  Hsueh-Ming Lu

IPC: H01L27/02 ,  H02H9/00

CPC classification number: H01L27/0262

Abstract: A latch-up-free ESD protection circuit using SCR is disclosed, in which an SCR is connected between the input pad and the negative power supply; a turn-on switch and a turn-off switch are connected between the positive power supply VDD (or the input pad) and the SCR; and a transistor gating circuit is connected to the turn-on switch and the turn-off switch to direct the operation of the SCR. When overvoltage stress develops over the input pad in the fast-transient mode, the turn-on switch enables the NPN transistor to switch on the SCR to form a discharging path for electrostatic discharge; and when overvoltage stress is released, the turn-off switch enables the PNP transistor to switch off the SCR, thus making it immune to any latch-up after the overvoltage stress is released, and having the advantages of fast triggering, low trigger voltage, no latch-up, and full ESD protection in the active and passive modes.

Abstract translation: 公开了一种使用SCR的无闩锁的ESD保护电路，其中SCR连接在输入焊盘和负电源之间; 在正电源V DD（或输入焊盘）和SCR之间连接有导通开关和关断开关; 并且晶体管门控电路连接到导通开关和关断开关以指导SCR的操作。 当在快速瞬态模式下在输入焊盘上产生过压应力时，导通开关使得NPN晶体管能够接通SCR以形成用于静电放电的放电路径; 当释放过压应力时，关断开关使PNP晶体管关断SCR，从而在过压应力释放后免受任何闭锁影响，具有触发快，触发电压低， 无闩锁和主动和被动模式下的全面ESD保护。

公开(公告)号：US20050260022A1

公开(公告)日：2005-11-24

申请号：US10916465

申请日：2004-08-12

Applicant: Ming Lu

Inventor： Ming Lu

IPC: B41J5/00 ,  B41J5/08 ,  G06F3/02 ,  H01H13/7057

CPC classification number: H01H13/7057 ,  H01H2229/034 ,  H01H2229/064 ,  H01H2233/004

Abstract: A key array structure comprises a key array constituted by connecting a plurality of key members arranged in an array, it is characterized in that an elastic element is connected between each two adjacent key members and a positioning hole or position holes is or are disposed in the key member. The elastic member disposed between each two adjacent key members of the key array structure according to the present invention has a cushioning effect to adjust the deformation of the key array caused from the processes such as heat baking while manufacturing so as to allow the positioning hole in each key member to be precisely positioned with a corresponding position pin on a relative member.

Abstract translation: 键阵列结构包括通过连接排列成阵列的多个键构件构成的键阵列，其特征在于，弹性元件连接在每个两个相邻的键构件之间，并且定位孔或位置孔设置在 主要成员。 设置在根据本发明的键阵列结构的每个两个相邻的键构件之间的弹性构件具有缓冲效果，以调节由制造过程中的热烘烤等过程引起的键阵列的变形，从而允许定位孔 每个键构件被精确地定位在相对构件上的相应的位置销。

公开(公告)号：US20050089764A1

公开(公告)日：2005-04-28

申请号：US10693989

申请日：2003-10-22

Applicant: Ming Lu ,  Bin-Chang Chang ,  Li-Wei Kung

Inventor： Ming Lu ,  Bin-Chang Chang ,  Li-Wei Kung

IPC: G03C5/00 ,  G03F9/00

CPC classification number: G03F1/30 ,  G03F1/28

Abstract: A phase shift mask comprises a transparent substrate having a patterned opaque material layer formed thereupon to form a non-transmissive region of the transparent substrate and an adjoining transmissive region of the transparent substrate. A pit is formed within the transmissive region of the transparent substrate. The pit has a stepped sidewall such as to provide the phase shift mask with enhanced optical performance. The phase shift mask may be fabricated employing a self aligned method.

Abstract translation: 相移掩模包括具有在其上形成的图案化不透明材料层的透明基板，以形成透明基板的非透射区域和透明基板的相邻透射区域。 在透明基板的透射区域内形成凹坑。 凹坑具有阶梯式侧壁，以提供具有增强的光学性能的相移掩模。 可以使用自对准方法来制造相移掩模。

公开(公告)号：US20050074186A1

公开(公告)日：2005-04-07

申请号：US10870968

申请日：2004-06-21

Applicant: Zhi-Ming Lu ,  Kun-Wei Lin

Inventor： Zhi-Ming Lu ,  Kun-Wei Lin

IPC: G06K9/32 ,  G06T3/40 ,  H04N5/00

CPC classification number: G06T3/4007

Abstract: A directional interpolation method and device for increasing resolution of an image is disclosed. The device includes an input terminal, a memory, a texture analysis module, a texture variance consistence module and an interpolation module. The input terminal receives signals representing the pixels of the image. The memory stores the pixels in row direction. The texture analysis module obtains a monotone variation area by taking the position as a center. The texture variance consistence module computes all directional texture variances in a closest upper and a closest lower rows of pixels within the monotone variation area in the case of taking the position as a center and accordingly finds two pixels having texture variance consistence. The interpolation module finds a value of pixel to be interpolated to the position through a median filter in accordance with the two pixels and their neighbor pixels.

Abstract translation: 公开了一种用于增加图像分辨率的方向插值方法和装置。 该装置包括输入端子，存储器，纹理分析模块，纹理方差一致模块和内插模块。 输入端子接收表示图像像素的信号。 存储器以行方向存储像素。 纹理分析模块通过以该位置为中心来获得单调变化区域。 在将该位置作为中心的情况下，纹理方差一致性模块计算单调变化区域内的最接近的上部和最接近的较低像素行中的所有方向纹理方差，因此找到具有纹理方差一致性的两个像素。 内插模块根据两个像素及其相邻像素，通过中值滤波器找到要插值的像素的值。

公开(公告)号：US20050063315A1

公开(公告)日：2005-03-24

申请号：US10665611

申请日：2003-09-19

Applicant: Tsao-Tsen Chen ,  Gang Li ,  Ming Lu ,  Martin Meyers

Inventor： Tsao-Tsen Chen ,  Gang Li ,  Ming Lu ,  Martin Meyers

IPC: H04L12/56 ,  H04Q7/00

CPC classification number: H04W28/18

Abstract: ntion is directed to the management of data burst requests. In iethod of the invention operates to determine a measure of one or parameters, which in an advantageous embodiment are the input z amount of data available in the input data buffer at the beginning t. The invention then proceeds to the selection of an operating data burst as a function of the input data parameter measures. In an nbodiment, the operating data rate is determined by computing the red data rate as a function of the input data rate and the data content fer at the beginning of the data burst, with the operating data rate lowest supported system data rate that is equal to or greater than the ed data rate. In a further step, the invention proceeds to a selection r the data burst from the burst durations supported by the wireless ction of the selected operating data rate and an end-of-burst data er. Advantageously, the system duration is selected that that, when selected operating data rate, provides a minimum end-of-burst data

公开(公告)号：US06785227B1

公开(公告)日：2004-08-31

申请号：US09568666

申请日：2000-05-11

Applicant: Ming Lu ,  Robert C. Qiu ,  Pengfei Zhu

Inventor： Ming Lu ,  Robert C. Qiu ,  Pengfei Zhu

IPC: H04L100

CPC classification number: H04W52/267 ,  H04W24/00 ,  H04W28/24 ,  H04W52/24 ,  H04W52/265 ,  H04W72/087

Abstract: A method and apparatus are provided for dynamically controlling a high speed wireless communication system capable of transmitting a message via a communication channel, to minimize the transmission power necessary for a single job and thereby increase system capacity. The communication channel is characterized by performance characteristics curves and physical channel characteristics curves. Channel conditions are sampled to model the performance characteristic curvers. Upon determining a minimum throughput to meet a Quality of Service requirement for user application, a first set of data pairs that correspond to the minimum throughput are determined from the performance characteristics curves. That first set of data pairs is in mapped to the physical channel characteristic curver and the data pair corresponding to minimum transmission power is then selected.

Abstract translation: 提供了一种方法和装置，用于动态地控制能够经由通信信道发送消息的高速无线通信系统，以最小化单个作业所需的传输功率，从而提高系统容量。 通信通道的特点是性能特征曲线和物理通道特性曲线。 对通道条件进行采样以对性能特征曲线进行建模。 在确定满足用户应用的服务质量要求的最小吞吐量时，根据性能特性曲线确定对应于最小吞吐量的第一组数据对。 第一组数据对映射到物理信道特征曲线，然后选择对应于最小发射功率的数据对。

公开(公告)号：US06652666B2

公开(公告)日：2003-11-25

申请号：US09847631

申请日：2001-05-02

Applicant: Ching-Tien Ma ,  Chen-Hsi Shih ,  Dian-Hau Chen ,  Gau-Ming Lu ,  Cho-Ching Chen

Inventor： Ching-Tien Ma ,  Chen-Hsi Shih ,  Dian-Hau Chen ,  Gau-Ming Lu ,  Cho-Ching Chen

IPC: B08B304

CPC classification number: G03F7/425 ,  G03F7/426 ,  H01L21/02052 ,  H01L21/31133 ,  Y10S134/902

Abstract: A wet dip method for photoresist and polymer stripping from a wafer surface without the need for a buffer solvent treatment step is disclosed. In the method, the wafer is first exposed to an etchant solution that is maintained at a temperature of at least 80° C. The wafer is then cooled in a room temperature air for a sufficient length of time until the temperature of the wafer reaches substantially room temperature. The wafer is then rinsed in a rinsing step that includes a quick dump rinse and a final rinse with deionized water that is maintained at a temperature not higher than room temperature without first exposing the wafer to a buffer solvent such as that required in a conventional wet dip method.

公开(公告)号：US06596611B2

公开(公告)日：2003-07-22

申请号：US09846932

申请日：2001-05-01

Applicant: Ming Lu ,  Szu-Wei Lu

Inventor： Ming Lu ,  Szu-Wei Lu

IPC: H01L21301

CPC classification number: H01L24/12 ,  H01L23/3114 ,  H01L24/11 ,  H01L2224/0231 ,  H01L2224/0401 ,  H01L2224/05124 ,  H01L2224/05147 ,  H01L2224/1147 ,  H01L2224/13099 ,  H01L2924/01013 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01078 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/14 ,  H01L2924/351 ,  H01L2924/00 ,  H01L2924/00014 ,  H01L2924/013

Abstract: A method for forming wafer level package that has a serpentine-shaped electrode formed along a scribe line in-between two adjacent IC dies and the package formed are disclosed. In the method, each of the I/O redistribution lines connecting from an I/O redistribution pad is connected to a serpentine-shaped electrode for providing electrical communication during a subsequent electro-deposition process for forming a solder bump on the corresponding I/O redistribution pad. During a dicing operation of the wafer level package, a single cut through the center of the serpentine-shaped electrode can effect severance of all IC dies without possibility of any inter-die shorting or intra-die shorting.

公开(公告)号：US06455433B1

公开(公告)日：2002-09-24

申请号：US09821987

申请日：2001-03-30

Applicant: Yao-Chi Chang ,  Kao-Ming Lu

Inventor： Yao-Chi Chang ,  Kao-Ming Lu

IPC: H01L2100

CPC classification number: H01L29/6659 ,  H01L21/31144 ,  H01L29/7833

Abstract: A method for forming sidewall spacers with square shoulders on polysilicon gates and the structure formed by the method are disclosed. In the method, a polysilicon gate is first formed on a silicon substrate wherein the gate has a silicon nitride pad on top. A conformal silicon nitride layer is then blanket deposited on top of the structure followed by the deposition of a silicon oxide layer on top of the conformal silicon nitride layer. The silicon oxide layer is then planarized until a top of the conformal silicon nitride layer is exposed. The conformal silicon nitride layer and the silicon nitride pad are then wet etched away to expose the polysilicon gate by using the silicon oxide layer as a mask. After a photoresist layer is coated and etched-back such that only a cavity formed by the silicon oxide layer, the polysilicon gate and the conformal silicon nitride layer is filled with the photoresist, the silicon oxide layer is wet etched away by an etchant such as HF. The square-shouldered sidewall spacers are then formed by first anisotropically etching the first silicon nitride layer not masked by the photoresist layer and then by a wet etching step to remove the photoresist layer.

Abstract translation: 公开了一种在多晶硅栅极上形成具有方形肩的侧壁间隔物的方法和由该方法形成的结构。 在该方法中，首先在硅衬底上形成多晶硅栅极，其中栅极顶部具有氮化硅衬垫。 然后将共形氮化硅层覆盖沉积在结构的顶部上，随后在共形氮化硅层的顶部上沉积氧化硅层。 然后将氧化硅层平坦化直到共形氮化硅层的顶部露出。 然后通过使用氧化硅层作为掩模，将保形氮化硅层和氮化硅焊盘湿法蚀刻掉以暴露多晶硅栅极。 在光致抗蚀剂层被涂覆和蚀刻后，使得仅由氧化硅层，多晶硅栅极和共形氮化硅层形成的空腔被光致抗蚀剂填充，氧化硅层被蚀刻剂湿蚀刻掉，例如 HF。 然后通过首先各向异性蚀刻未被光致抗蚀剂层掩蔽的第一氮化硅层，然后通过湿蚀刻步骤去除光致抗蚀剂层，形成方肩的侧壁间隔物。

公开(公告)号：US6030872A

公开(公告)日：2000-02-29

申请号：US241545

申请日：1999-02-01

Applicant: Jau-Hone Lu ,  Shu-Ying Lu ,  Chang-Ming Lu ,  Ya-Ling Hung

Inventor： Jau-Hone Lu ,  Shu-Ying Lu ,  Chang-Ming Lu ,  Ya-Ling Hung

IPC: H01L21/8234 ,  H01L21/336

CPC classification number: H01L21/823462 ,  Y10S438/981

Abstract: A method for fabricating a mixed-mode device. A first gate oxide layer and a second gate oxide layer are formed. The polysilicon layer is used as a mask to pattern the gate oxide layers. Additionally, a top electrode is formed during the first gate oxide layer is patterned. A bottom electrode is formed during the second gate oxide layer is patterned. The first gate oxide layer and the second gate oxide layer are formed by a single oxidation operation, thus thicknesses of the first gate oxide layer and the second oxide layer can be effectively controlled.

Abstract translation: 一种混合模式装置的制造方法。 形成第一栅极氧化物层和第二栅极氧化物层。 多晶硅层用作掩模以对栅极氧化物层进行图案化。 此外，在第一栅极氧化物层被图案化时形成顶部电极。 在第二栅极氧化层被图案化时形成底部电极。 第一栅极氧化物层和第二栅极氧化物层通过单次氧化操作形成，从而能够有效地控制第一栅极氧化物层和第二氧化物层的厚度。