公开(公告)号：US08369066B2

公开(公告)日：2013-02-05

申请号：US12713398

申请日：2010-02-26

申请人： Ching-Feng Lin ,  Yui-Hsin Fran ,  Chi-Hao Chiu ,  Ming-Tsung Chen ,  Cheng-Wei Lai ,  Chun-Chia Huang

发明人： Ching-Feng Lin ,  Yui-Hsin Fran ,  Chi-Hao Chiu ,  Ming-Tsung Chen ,  Cheng-Wei Lai ,  Chun-Chia Huang

IPC分类号： H01G9/00

CPC分类号： H01G9/012 ,  H01G2/06 ,  H01G9/15

摘要： A lamellar stacked solid electrolytic capacitor includes a plurality of capacitor units, a substrate unit and a package unit. Each capacitor unit is composed of a negative foil, an isolation paper with conductive polymer substance, a positive foil, an isolation paper with conductive polymer substance and a negative foil that are stacked onto each other in sequence, the positive foils of the capacitor units are electrically connected to each other, the negative foils of the capacitor units are electrically connected to each other, and the positive foils and the negative foils are insulated from each other. The substrate unit has a positive guiding substrate electrically connected to the positive foils of the capacitor units and a negative guiding substrate electrically connected to the negative foils of the capacitor units. The package unit covers the capacitor units and one part of the substrate unit.

摘要翻译： 片状堆叠固体电解电容器包括多个电容器单元，基板单元和封装单元。 每个电容器单元由负箔，具有导电聚合物物质的隔离纸，正箔，具有导电聚合物物质的隔离纸和负箔依次堆叠组成，电容器单元的正箔是 彼此电连接，电容器单元的负箔彼此电连接，并且正箔和负箔彼此绝缘。 基板单元具有电连接到电容器单元的正箔的正引导基板和电连接到电容器单元的负箔的负引导基板。 封装单元覆盖电容器单元和衬底单元的一部分。

公开(公告)号：US20130007666A1

公开(公告)日：2013-01-03

申请号：US13279341

申请日：2011-10-24

申请人： WEI SONG ,  XIAO-GUANG LI ,  HAN-CHE WANG ,  MING-TSUNG CHEN

发明人： WEI SONG ,  XIAO-GUANG LI ,  HAN-CHE WANG ,  MING-TSUNG CHEN

IPC分类号： G06F3/048

CPC分类号： G06F3/04883 ,  G06F3/0485

摘要： An electronic device with a touch screen device selectively displaying one of a plurality of desktop screens is disclosed. Each desktop screen includes function icons and page icons associated with desktop screens. The electronic device further includes a function icon sensing module, a function icon moving module, a page icon sensing module and a page flipping module. The function icon sensing module senses touch on the function icons. The function icon moving module moves the function icon when an icon move operation has been performed. The page icon sensing module senses the touch on a page icon. The page flipping module controls the touch screen device to display a desired desktop screen associated with the selected page icon and add the selected function icon to the desired desktop screen. A method of moving function icon and one or more computer readable storage media comprising computer executable instructions are also disclosed.

摘要翻译： 公开了一种具有选择性地显示多个桌面屏幕之一的触摸屏设备的电子设备。 每个桌面屏幕包括与桌面屏幕相关联的功能图标和页面图标。 电子设备还包括功能图标感测模块，功能图标移动模块，页面图标感测模块和翻页模块。 功能图标感应模块检测功能图标上的触摸。 当执行图标移动操作时，功能图标移动模块移动功能图标。 页面图标感测模块感测页面图标上的触摸。 页面翻转模块控制触摸屏设备以显示与所选页面图标相关联的期望的桌面屏幕，并将所选功能图标添加到所需的桌面屏幕。 还公开了一种移动功能图标的方法和包括计算机可执行指令的一个或多个计算机可读存储介质。

公开(公告)号：US08164141B2

公开(公告)日：2012-04-24

申请号：US12884198

申请日：2010-09-17

申请人： Po-Chao Tsao ,  Chang-Chi Huang ,  Ming-Tsung Chen ,  Feng-Yi Chang ,  Pei-Yu Chou ,  Jiunn-Hsiung Liao ,  Chih-Wen Feng ,  Ying-Chih Lin

发明人： Po-Chao Tsao ,  Chang-Chi Huang ,  Ming-Tsung Chen ,  Feng-Yi Chang ,  Pei-Yu Chou ,  Jiunn-Hsiung Liao ,  Chih-Wen Feng ,  Ying-Chih Lin

IPC分类号： H01L29/78

CPC分类号： H01L21/31144 ,  H01L21/76802 ,  H01L21/76831 ,  H01L23/485

摘要： An opening structure includes a semiconductor substrate, at least one dielectric layer disposed on the semiconductor substrate, wherein the dielectric layer has a plurality of openings exposing the semiconductor substrate, and each of the openings has a sidewall, a dielectric thin film covering at least a portion of the sidewall of each of the openings, and a metal layer filled in the openings.

摘要翻译： 开口结构包括半导体衬底，设置在半导体衬底上的至少一个电介质层，其中所述电介质层具有暴露所述半导体衬底的多个开口，并且每个所述开口具有侧壁，至少覆盖至少一个的电介质薄膜 每个开口的侧壁的一部分，以及填充在开口中的金属层。

公开(公告)号：US20120001338A1

公开(公告)日：2012-01-05

申请号：US13234159

申请日：2011-09-16

申请人： Po-Chao Tsao ,  Chang-Chi Huang ,  Ming-Tsung Chen ,  Feng-Yi Chang ,  Pei-Yu Chou ,  Jiunn-Hsiung Liao ,  Chih-Wen Feng ,  Ying-Chih Lin

发明人： Po-Chao Tsao ,  Chang-Chi Huang ,  Ming-Tsung Chen ,  Feng-Yi Chang ,  Pei-Yu Chou ,  Jiunn-Hsiung Liao ,  Chih-Wen Feng ,  Ying-Chih Lin

IPC分类号： H01L23/48

CPC分类号： H01L21/31144 ,  H01L21/76802 ,  H01L21/76831 ,  H01L23/485

摘要： An opening structure is disclosed. The opening structure includes: a semiconductor substrate; at least one dielectric layer disposed on the semiconductor substrate, wherein the dielectric layer has a plurality of openings exposing the semiconductor substrate, and each of the openings has a sidewall; a dielectric thin film covering at least a portion of the sidewall of each of the openings; an etch stop layer disposed between the semiconductor substrate and the dielectric layer and extending partially into the openings to isolate the dielectric thin film from the semiconductor substrate; and a metal layer filled in the openings.

摘要翻译： 公开了一种开口结构。 开口结构包括：半导体衬底; 设置在所述半导体衬底上的至少一个电介质层，其中所述电介质层具有暴露所述半导体衬底的多个开口，并且每个所述开口具有侧壁; 覆盖每个开口的侧壁的至少一部分的电介质薄膜; 蚀刻停止层，设置在所述半导体衬底和所述电介质层之间并且部分地延伸到所述开口中以将所述电介质薄膜与所述半导体衬底隔离; 以及填充在开口中的金属层。

公开(公告)号：US20110186215A1

公开(公告)日：2011-08-04

申请号：US12699064

申请日：2010-02-03

申请人： Chin-Sen LAI ,  Ming-Tsung Chen

发明人： Chin-Sen LAI ,  Ming-Tsung Chen

IPC分类号： B32B38/10 ,  B32B43/00

CPC分类号： B32B38/10 ,  B32B43/00

摘要： A method for laminating a film on a wafer includes a pre-cutting step: pre-cutting a dry film for fitting a size wafer size; a pre-attaching step: moving and pre-attaching the cut dry film on the wafer for corresponding the cut dry film and the wafer; a laminating step: laminating the cut dry film on the wafer with heating for fixing the cut dry film on the wafer. A flattening step: vertically and rigidly laminating the cut dry film on the wafer with heating again for flattening the cut dry film on the wafer.

摘要翻译： 用于在晶片上层压膜的方法包括预切割步骤：预切割用于调整晶片尺寸的干膜; 预先安装步骤：将切割的干膜移动并预先安装在晶片上以对应于切割的干膜和晶片; 层压步骤：通过加热将切割的干膜层压在晶片上，以将切割的干膜固定在晶片上。 平整步骤：再次加热，将切割的干膜垂直且刚性地层叠在晶片上，以使晶片上的切割干膜变平。

公开(公告)号：US20100308220A1

公开(公告)日：2010-12-09

申请号：US12480117

申请日：2009-06-08

申请人： Ling-Chun Chou ,  Ming-Tsung Chen ,  Po-Chao Tsao ,  Hsi-Hua Liu ,  Shuen-Cheng Lei ,  Ming-Yi Lin

发明人： Ling-Chun Chou ,  Ming-Tsung Chen ,  Po-Chao Tsao ,  Hsi-Hua Liu ,  Shuen-Cheng Lei ,  Ming-Yi Lin

IPC分类号： G01N23/00

CPC分类号： H01L22/12 ,  H01L22/34

摘要： The method for in-line monitoring a wafer is described as follows. A wafer is provided, and at least one inspection structure is then formed on the wafer in the following steps. An N-well region and a P-well region are formed in the wafer, wherein the N-well region and the P-well region are separated from each other. A gate on each of the N-well region and the P-well region is formed. A P-type doped region is respectively formed in the N-well region and in the P-well region at both sides of the gates. A first contact plug is formed on each P-type doped region, and second contact plug is formed on each gate. Afterwards, a defect inspection is conducted utilizing an electron beam inspection (EBI) system, such that a short between each first contact plug and each gate is determined.

摘要翻译： 在线监视晶片的方法如下所述。 提供晶片，然后在以下步骤中在晶片上形成至少一个检查结构。 在晶片中形成N阱区域和P阱区域，其中N阱区域和P阱区域彼此分离。 形成N阱区域和P阱区域中的每一个的栅极。 P型掺杂区域分别形成在栅极两侧的N阱区域和P阱区域中。 在每个P型掺杂区域上形成第一接触插塞，并且在每个栅极上形成第二接触插塞。 然后，利用电子束检查（EBI）系统进行缺陷检查，使得确定每个第一接触插塞和每个门之间的短路。

公开(公告)号：US07696086B2

公开(公告)日：2010-04-13

申请号：US11309201

申请日：2006-07-13

申请人： Yu-Hao Hsu ,  Ming-Tsung Chen

发明人： Yu-Hao Hsu ,  Ming-Tsung Chen

IPC分类号： H01L21/00

CPC分类号： H01L21/76895 ,  H01L21/76807 ,  H01L21/76838 ,  H01L23/5226 ,  H01L23/53223 ,  H01L23/53238 ,  H01L23/53252 ,  H01L23/5329 ,  H01L23/53295 ,  H01L2924/0002 ,  H01L2924/00

摘要： An interconnect structure is described, disposed on a substrate with a conductive part thereon and including a dielectric layer, a composite plug and a conductive line. The dielectric layer is disposed on the substrate covering the conductive part. The composite plug is disposed in the dielectric layer electrically connecting with the conductive part, and includes a first plug and a second plug on the first plug, wherein the material or the critical dimension of the second plug is different from that of the first plug. The conductive line is disposed on the dielectric layer electrically connecting with the composite plug.

摘要翻译： 描述了一种互连结构，其设置在其上具有导电部分的基板上，并且包括电介质层，复合插塞和导电线。 电介质层设置在覆盖导电部件的基板上。 复合插头设置在与导电部件电连接的电介质层中，并且包括第一插头和第一插头上的第二插头，其中第二插头的材料或临界尺寸与第一插头的材料或临界尺寸不同。 导电线设置在与复合插头电连接的电介质层上。

公开(公告)号：US07572722B2

公开(公告)日：2009-08-11

申请号：US11685209

申请日：2007-03-13

申请人： Yi-Wei Chen ,  Chao-Ching Hsieh ,  Yi-Yiing Chiang ,  Tzung-Yu Hung ,  Yu-Lan Chang ,  Po-Chao Tsao ,  Chang-Chi Huang ,  Ming-Tsung Chen

发明人： Yi-Wei Chen ,  Chao-Ching Hsieh ,  Yi-Yiing Chiang ,  Tzung-Yu Hung ,  Yu-Lan Chang ,  Po-Chao Tsao ,  Chang-Chi Huang ,  Ming-Tsung Chen

IPC分类号： H01L21/3205

CPC分类号： H01L29/665 ,  H01L21/324 ,  H01L29/4933

摘要： A semiconductor device having nickel silicide and a method for fabricating nickel silicide. A semiconductor substrate having a plurality of doped regions is provided. Subsequently, a nickel layer is formed on the semiconductor substrate, and a first rapid thermal process (RTP) is performed to react the nickel layer with the doped regions disposed there under. Thereafter, the unreacted nickel layer is removed, and a second rapid thermal process is performed to form a semiconductor device having nickel silicide. The second rapid thermal process is a spike anneal process whose process temperature is between 400 and 600° C.

摘要翻译： 具有硅化镍的半导体器件和制造硅化镍的方法。 提供具有多个掺杂区域的半导体衬底。 随后，在半导体衬底上形成镍层，并进行第一快速热处理（RTP）以使镍层与设置在其下方的掺杂区域反应。 此后，除去未反应的镍层，进行第二快速热处理以形成具有硅化镍的半导体器件。 第二快速热处理是工艺温度在400和600℃之间的尖峰退火工艺。

公开(公告)号：US20080230917A1

公开(公告)日：2008-09-25

申请号：US11686740

申请日：2007-03-15

申请人： Ling-Chun Chou ,  Ming-Tsung Chen ,  Po-Chao Tsao

发明人： Ling-Chun Chou ,  Ming-Tsung Chen ,  Po-Chao Tsao

IPC分类号： H01L23/48

CPC分类号： H01L21/76897 ,  H01L21/28518 ,  H01L21/76831 ,  H01L21/76895 ,  H01L23/485 ,  H01L2924/0002 ,  H01L2924/00

摘要： A method of fabricating a self-aligned contact is provided. A first dielectric layer is formed on a substrate having a contact region therein. Next, a lower hole corresponding to the contact region is formed in the first dielectric layer. Thereafter, a second dielectric layer is formed on the first dielectric layer, and then an upper hole self-aligned to and communicated with the lower hole is formed in the second dielectric layer, wherein the upper hole and the lower hole constitute a self-aligned contact hole. Afterwards, the self-aligned contact hole is filled with a conductive layer.

摘要翻译： 提供一种制造自对准接触的方法。 在其中具有接触区域的基板上形成第一电介质层。 接下来，在第一电介质层中形成与接触区域对应的下孔。 此后，在第一电介质层上形成第二电介质层，然后在第二电介质层中形成自对准并与下孔连通的上孔，其中上孔和下孔构成自对准 接触孔。 然后，自对准接触孔填充有导电层。

公开(公告)号：US20070181955A1

公开(公告)日：2007-08-09

申请号：US11691485

申请日：2007-03-26

申请人： Ming-Tsung Chen ,  Chang-Chi Huang ,  Po-Chao Tsao

发明人： Ming-Tsung Chen ,  Chang-Chi Huang ,  Po-Chao Tsao

IPC分类号： H01L29/76

CPC分类号： H01L21/28518 ,  H01L21/26506 ,  H01L29/665 ,  H01L29/6656 ,  H01L29/66628 ,  H01L29/7834

摘要： A metal oxide semiconductor (MOS) transistor is disclosed. The MOS transistor includes: a semiconductor substrate; a gate disposed on the semiconductor substrate, wherein the gate comprises two sidewalls; a spacer formed on the sidewalls of the gate; a source/drain region disposed in the semiconductor substrate; a silicide layer disposed on top of the gate and the surface of the source/drain region; and a retarded interface layer disposed in the junction between the silicide layer and the gate and source/drain region.

摘要翻译： 公开了一种金属氧化物半导体（MOS）晶体管。 MOS晶体管包括：半导体衬底; 设置在所述半导体衬底上的栅极，其中所述栅极包括两个侧壁; 形成在栅极的侧壁上的间隔物; 设置在所述半导体衬底中的源/漏区; 设置在栅极的顶部和源极/漏极区域的表面上的硅化物层; 以及设置在硅化物层与栅极和源极/漏极区之间的结中的延迟界面层。