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    Methods for fabricating semiconductor devices
    61.
    发明授权
    Methods for fabricating semiconductor devices 失效
    制造半导体器件的方法

    公开(公告)号：US06852592B2

    公开(公告)日：2005-02-08

    申请号：US10452347

    申请日：2003-06-02

    Applicant: Sung-Kwon Lee ,  Min-Suk Lee ,  Sang-Ik Kim

    Inventor： Sung-Kwon Lee ,  Min-Suk Lee ,  Sang-Ik Kim

    IPC: H01L21/306 ,  H01L21/308 ,  H01L21/311 ,  H01L21/768 ,  H01L21/8242 ,  H01L27/108

    CPC classification number: H01L27/10855 ,  H01L21/31111 ,  H01L21/31116 ,  H01L21/76802 ,  H01L21/76804 ,  H01L21/76829 ,  H01L27/10814 ,  H01L27/10885

    Abstract: A method for fabricating a semiconductor device includes forming a plurality of first plugs contacted to a substrate by passing through a first inter-layer insulation layer; forming a second inter-layer insulation layer on the first plugs; forming a conductive pattern contacted to a group of the first plugs by etching selectively the second inter-layer insulation layer; and forming a contact hole exposing a surface of the first plug that is not contacted to the conductive pattern by etching selectively the second insulation layer with use of a dry-type and wet-type etch process, wherein an attack barrier layer is formed on between the first inter-layer insulation layer and the second inter-layer insulation layer to thereby prevent an incidence of attack to the first interlayer insulation layer contacted to the first plug during the wet-type etch process for forming the contact hole.

    Abstract translation: 一种制造半导体器件的方法包括：通过穿过第一层间绝缘层形成与衬底接触的多个第一插塞; 在所述第一插塞上形成第二层间绝缘层; 通过选择性地蚀刻第二层间绝缘层来形成与一组第一插塞接触的导电图案; 以及通过使用干式和湿式蚀刻工艺选择性地蚀刻所述第二绝缘层，形成暴露所述第一插塞的未与所述导电图案接触的表面的接触孔，其中， 第一层间绝缘层和第二层间绝缘层，从而防止在用于形成接触孔的湿式蚀刻工艺期间对与第一插塞接触的第一层间绝缘层的攻击入射。

    Method of fabricating a semiconductor device having a plug
    64.
    发明授权
    Method of fabricating a semiconductor device having a plug 失效
    制造具有插头的半导体器件的方法

    公开(公告)号：US08202795B2

    公开(公告)日：2012-06-19

    申请号：US11965966

    申请日：2007-12-28

    Applicant: Min-Suk Lee ,  Won-Kyu Kim

    Inventor： Min-Suk Lee ,  Won-Kyu Kim

    IPC: H01L21/44 ,  H01L21/4763

    CPC classification number: H01L21/76897 ,  H01L21/76895 ,  H01L27/10823 ,  H01L27/10876 ,  H01L27/10894 ,  H01L27/10897

    Abstract: A method of fabricating a semiconductor device, the method includes forming gate patterns on a substrate, recessing the substrate between the gate patterns, thereby forming a first resulting structure including recesses, forming a gate spacer layer on an entire surface of the first resulting structure including the gate patterns, etching the gate spacer layer at a bottom of the recess, and forming a plug on the recess, thereby forming a second resulting structure including the plug.

    Abstract translation: 一种制造半导体器件的方法，该方法包括在衬底上形成栅极图案，使衬底在栅极图案之间凹陷，从而形成包括凹槽的第一结果结构，在第一结果结构的整个表面上形成栅极间隔层，包括 栅极图案，在凹部的底部蚀刻栅极间隔层，并且在凹部上形成插塞，从而形成包括插头的第二结果结构。

    Method for fabricating semiconductor device
    65.
    发明授权
    Method for fabricating semiconductor device 失效
    制造半导体器件的方法

    公开(公告)号：US07700493B2

    公开(公告)日：2010-04-20

    申请号：US11904401

    申请日：2007-09-27

    Applicant: Sung-Kwon Lee ,  Min-Suk Lee

    Inventor： Sung-Kwon Lee ,  Min-Suk Lee

    IPC: H01L21/302

    CPC classification number: H01L21/76897 ,  H01L21/31116 ,  H01L21/31144

    Abstract: A method for fabricating a semiconductor device includes forming a first pattern over a substrate, forming an oxide-based layer over the first pattern, forming a hard mask layer over the oxide-based layer, etching the hard mask layer at a first substrate temperature, and etching the oxide-based layer to form a second pattern, wherein the oxide-based layer is etched at a second substrate temperature which is greater than the first substrate temperature using a gas including fluorine (F) and carbon (C) as a main etch gas.

    Abstract translation: 一种制造半导体器件的方法包括在衬底上形成第一图案，在第一图案上形成氧化物基层，在氧化物基层上形成硬掩模层，在第一衬底温度下蚀刻硬掩模层， 并且蚀刻所述氧化物基层以形成第二图案，其中所述氧化物基层在使用包含氟（F）和碳（C））为主要气体的第二基板温度下蚀刻，所述第二基板温度大于所述第一基板温度 蚀刻气体。

    METHOD FOR FABRICATING SEMICONDUCTOR DEVICE
    67.
    发明申请
    METHOD FOR FABRICATING SEMICONDUCTOR DEVICE 失效
    制造半导体器件的方法

    公开(公告)号：US20090004855A1

    公开(公告)日：2009-01-01

    申请号：US11965966

    申请日：2007-12-28

    Applicant: Min-Suk LEE ,  Won-Kyu KIM

    Inventor： Min-Suk LEE ,  Won-Kyu KIM

    IPC: H01L21/768

    CPC classification number: H01L21/76897 ,  H01L21/76895 ,  H01L27/10823 ,  H01L27/10876 ,  H01L27/10894 ,  H01L27/10897

    Abstract: A method of fabricating a semiconductor device, the method includes forming gate patterns on a substrate, recessing the substrate between the gate patterns, thereby forming a first resulting structure including recesses, forming a gate spacer layer on an entire surface of the first resulting structure including the gate patterns, etching the gate spacer layer at a bottom of the recess, and forming a plug on the recess, thereby forming a second resulting structure including the plug.

    Abstract translation: 一种制造半导体器件的方法，该方法包括在衬底上形成栅极图案，使衬底在栅极图案之间凹陷，从而形成包括凹槽的第一结果结构，在第一结果结构的整个表面上形成栅极间隔层，包括 栅极图案，在凹部的底部蚀刻栅极间隔层，并且在凹部上形成插塞，从而形成包括插头的第二结果结构。

    Method for fabricating semiconductor device
    68.
    发明申请
    Method for fabricating semiconductor device 失效
    制造半导体器件的方法

    公开(公告)号：US20080311735A1

    公开(公告)日：2008-12-18

    申请号：US12006142

    申请日：2007-12-31

    Applicant: Min-Suk Lee

    Inventor： Min-Suk Lee

    IPC: H01L21/28

    CPC classification number: H01L21/76897 ,  H01L27/10894

    Abstract: A method for fabricating a semiconductor device includes forming at least one gate pattern over a substrate, forming a first insulation layer over the gate patterns and the substrate, etching the first insulation layer in a peripheral region to form at least one gate pattern spacer in the peripheral region, forming a second insulation layer over the substrate structure, etching the second insulation layer in a cell region to a given thickness, forming an insulation structure over the substrate structure, and etching the insulation structure, the etched first insulation layer and second insulation layer in the cell region to form a contact hole.

    Abstract translation: 一种用于制造半导体器件的方法包括在衬底上形成至少一个栅极图案，在栅极图案和衬底之上形成第一绝缘层，在周边区域蚀刻第一绝缘层，以形成至少一个栅极图案间隔物 在衬底结构上形成第二绝缘层，将单元区域中的第二绝缘层蚀刻到给定厚度，在衬底结构上形成绝缘结构，以及蚀刻绝缘结构，蚀刻的第一绝缘层和第二绝缘层 层形成接触孔。

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