公开(公告)号：US20150069558A1

公开(公告)日：2015-03-12

申请号：US14203249

申请日：2014-03-10

Applicant: Masahiko NAKAYAMA ,  Tadashi KAI ,  Masaru TOKO ,  Hiroaki YODA ,  Hyung Suk LEE ,  Jae Geun OH ,  Choon Kun RYU ,  Min Suk LEE

Inventor： Masahiko NAKAYAMA ,  Tadashi KAI ,  Masaru TOKO ,  Hiroaki YODA ,  Hyung Suk LEE ,  Jae Geun OH ,  Choon Kun RYU ,  Min Suk LEE

IPC: H01L43/02 ,  H01L43/12

CPC classification number: H01L43/02 ,  G11C11/15 ,  G11C11/16 ,  G11C11/161 ,  G11C11/1659 ,  G11C11/5607 ,  H01L27/222 ,  H01L27/228 ,  H01L27/2463 ,  H01L43/08 ,  H01L43/10 ,  H01L43/12 ,  H01L45/04

Abstract: According to one embodiment, a magnetic memory is disclosed. The memory includes a conductive layer containing a first metal material, a stacked body above the conductive layer, and including a first magnetization film containing a second metal material, a second magnetization film, and a tunnel barrier layer between the first magnetization film and the second magnetization film, and an insulating layer on a side face of the stacked body, and containing an oxide of the first metal material. The first magnetization film and/or the second magnetization film includes a first region positioned in a central portion, and a second region positioned in an edge portion and containing As, P, Ge, Ga, Sb, In, N, Ar, He, F, Cl, Br, I, Si, B, C, O, Zr, Tb, S, Se, or Ti.

Abstract translation: 根据一个实施例，公开了一种磁存储器。 该存储器包括一个包含第一金属材料的导电层，在该导电层上方的层叠体，并且包括一个第一磁化膜，该第一磁化膜含有第二金属材料，第二磁化膜和第一磁化膜与第二磁化膜之间的隧道势垒层 磁化膜和层叠体的侧面上的绝缘层，并且含有第一金属材料的氧化物。 第一磁化膜和/或第二磁化膜包括位于中心部分的第一区域和位于边缘部分中并且包含As，P，Ge，Ga，Sb，In，N，Ar，He的第二区域， F，Cl，Br，I，Si，B，C，O，Zr，Tb，S，Se或Ti。

公开(公告)号：US08642358B2

公开(公告)日：2014-02-04

申请号：US13315011

申请日：2011-12-08

Applicant: Min Suk Lee

Inventor： Min Suk Lee

IPC: H01L21/00 ,  G11C5/06

CPC classification number: H01L43/12 ,  G11C11/161

Abstract: A method for fabricating a semiconductor device includes forming a plurality of layers which are stacked as a bottom layer, an MTJ layer, and a top layer, patterning the top layer and the MTJ layer using an etch mask pattern to form a top layer pattern and an MTJ pattern, forming a carbon spacer on the sidewalls of the MTJ pattern and the top layer pattern to protect the MTJ pattern and the top layer pattern, and patterning the bottom layer using the carbon spacer and the etch mask pattern as an etch mask to form a bottom layer pattern.

Abstract translation: 一种用于制造半导体器件的方法包括：形成层叠为底层的多个层，MTJ层和顶层，使用蚀刻掩模图案对顶层和MTJ层进行图案化以形成顶层图案;以及 MTJ图案，在MTJ图案的侧壁上形成碳隔离物和顶层图案以保护MTJ图案和顶层图案，并使用碳间隔物和蚀刻掩模图案作为蚀刻掩模将底层图案化， 形成底层图案。

公开(公告)号：US08420408B2

公开(公告)日：2013-04-16

申请号：US13187782

申请日：2011-07-21

Applicant: Min Suk Lee ,  Byung Gu Gyun ,  Bo Kyoung Jung ,  Chang Hyup Shin

Inventor： Min Suk Lee ,  Byung Gu Gyun ,  Bo Kyoung Jung ,  Chang Hyup Shin

IPC: H01L43/08

CPC classification number: H01L29/82 ,  G11C11/161 ,  H01L43/12

Abstract: A method for manufacturing a semiconductor memory device includes sequentially depositing a bottom electrode layer, a magnetic tunnel junction (MTJ) layer, a first top electrode layer, a second top electrode layer and a mask layer, etching the mask layer and forming a mask pattern, etching the second top electrode layer and the first top electrode layer by using the mask pattern as an etch barrier, etching the MTJ layer by using the mask layer and the second top electrode layer as an etch barrier, and etching the bottom electrode layer by using the first top electrode layer as an etch barrier.

Abstract translation: 一种半导体存储器件的制造方法，包括依次沉积底部电极层，磁性隧道结（MTJ）层，第一顶部电极层，第二顶部电极层和掩模层，蚀刻掩模层并形成掩模图案 通过使用掩模图案作为蚀刻阻挡层蚀刻第二顶部电极层和第一顶部电极层，通过使用掩模层和第二顶部电极层作为蚀刻阻挡层来蚀刻MTJ层，并且通过 使用第一顶部电极层作为蚀刻阻挡层。

公开(公告)号：US07952278B2

公开(公告)日：2011-05-31

申请号：US12318461

申请日：2008-12-30

Applicant: Min-Suk Lee ,  Jong-Seo Choi ,  Matulevich Yuri ,  Suk-Ki Kim ,  Young-Su Kim ,  Deok-Hyun Kim ,  Hee-Young Chu ,  Soon-Sung Suh

Inventor： Min-Suk Lee ,  Jong-Seo Choi ,  Matulevich Yuri ,  Suk-Ki Kim ,  Young-Su Kim ,  Deok-Hyun Kim ,  Hee-Young Chu ,  Soon-Sung Suh

IPC: H01J17/49

CPC classification number: H01J11/40 ,  H01J11/12 ,  Y10T428/24479

Abstract: A protective layer of a plasma display panel includes smoky magnesium oxide, the smoky magnesium oxide having single crystal magnesium oxide with a plurality of cavities therein.

Abstract translation: 等离子体显示面板的保护层包括烟雾氧化镁，该烟雾氧化镁具有单晶氧化镁，其中具有多个空腔。

公开(公告)号：US20090004797A1

公开(公告)日：2009-01-01

申请号：US11965706

申请日：2007-12-27

Applicant: Min-Suk LEE

Inventor： Min-Suk LEE

IPC: H01L21/336

CPC classification number: H01L29/66666 ,  H01L27/10876 ,  H01L27/10885 ,  H01L29/7827

Abstract: A method of fabricating a semiconductor device includes forming a plurality of pillars which are arranged on a substrate in a first direction and a second direction that intersects the first direction, thereby forming a resulting structure, forming a capping layer on the resulting structure including the pillars, removing the capping layer formed on the substrate between the pillars to expose the substrate between the pillars, thereby forming a resulting structure, forming a metal layer on the resulting structure, forming a silicide layer on the exposed substrate between the pillars by applying a first heat treatment to the metal layer, removing a non-reacted silicide layer, and forming an isolation trench in the substrate which is between rows of the pillars arranged in the first direction and is under the silicide layer to define bit lines which surround the pillars and are extended to the first direction.

Abstract translation: 制造半导体器件的方法包括：在与第一方向相交的第一方向和第二方向上形成布置在基板上的多个柱，从而形成所得到的结构，在所得到的结构上形成覆盖层，所述结构包括柱 去除在支柱之间形成在衬底上的覆盖层，以暴露柱之间的衬底，由此形成所得结构，在所得结构上形成金属层，通过施加第一衬底在所述柱之间的暴露衬底上形成硅化物层 对金属层进行热处理，去除未反应的硅化物层，以及在衬底中形成隔离沟槽，所述衬底位于沿着第一方向布置的柱的行之间，并且位于硅化物层下方以限定围绕柱的位线， 延伸到第一个方向。

公开(公告)号：US20080317944A1

公开(公告)日：2008-12-25

申请号：US12230108

申请日：2008-08-22

Applicant: Min-suk Lee ,  Jong-seo Choi ,  Suk-ki Kim ,  Jae-Hyuk Kim ,  Soon-sung Suh

Inventor： Min-suk Lee ,  Jong-seo Choi ,  Suk-ki Kim ,  Jae-Hyuk Kim ,  Soon-sung Suh

IPC: B05D5/12 ,  C09D1/00

CPC classification number: H01J11/40 ,  C04B35/04 ,  C04B35/653 ,  C04B2235/3272 ,  C04B2235/3275 ,  C04B2235/3279 ,  C04B2235/3281 ,  C04B2235/443 ,  C04B2235/445 ,  C23C30/00 ,  H01J11/12

Abstract: A protecting layer is formed of a magnesium oxide and at least one additional component selected from the group consisting of a copper component selected from copper and a copper oxide, a nickel component selected from nickel and a nickel oxide, a cobalt component selected from cobalt and a cobalt oxide, and an iron component selected from iron and an iron oxide; a composite for forming the protecting layer; a method of forming the protecting layer; and a plasma display panel including the protecting layer. The protecting layer, which is used in a PDP, protects an electrode and a dielectric layer from a plasma ion generated by a gaseous mixture of Ne and Xe, or He, Ne, and Xe, and discharge delay time and dependency of the discharge delay time on temperature can be decreased and sputtering resistance can be increased.

Abstract translation: 保护层由氧化镁和至少一种选自铜和氧化铜的铜成分，选自镍和氧化镍的镍成分，选自钴的钴成分和选自钴的钴成分组成的组中， 钴氧化物和选自铁和氧化铁的铁组分; 用于形成保护层的复合材料; 形成保护层的方法; 以及包括保护层的等离子体显示面板。 用于PDP中的保护层保护电极和电介质层免受由Ne和Xe或He，Ne和Xe的气体混合物产生的等离子体离子，并且放电延迟时间和放电延迟的依赖性 可以降低温度时间，并且可以提高溅射电阻。

公开(公告)号：US20070202691A1

公开(公告)日：2007-08-30

申请号：US11646473

申请日：2006-12-28

Applicant: Min-Suk Lee ,  Jae-Young Lee

Inventor： Min-Suk Lee ,  Jae-Young Lee

IPC: H01L21/4763

CPC classification number: H01L21/76897

Abstract: A method for fabricating a semiconductor device includes forming electrode patterns over a substrate, wherein the electrode patterns include a hard mask, forming a passivation layer on the electrode patterns, forming an insulation layer on the passivation layer, filling a space between the electrode patterns, planarizing the insulation layer until shoulder portions of the hard mask are planarized, forming a mask pattern on a resultant structure, and etching a portion of the insulation layer to form a contact hole.

Abstract translation: 一种用于制造半导体器件的方法包括在衬底上形成电极图案，其中电极图案包括硬掩模，在电极图案上形成钝化层，在钝化层上形成绝缘层，填充电极图案之间的空间， 平面化绝缘层，直到硬掩模的肩部平坦化，在所得结构上形成掩模图案，并蚀刻绝缘层的一部分以形成接触孔。

公开(公告)号：US07196004B2

公开(公告)日：2007-03-27

申请号：US10924720

申请日：2004-08-23

Applicant: Min-Suk Lee ,  Sung-Kwon Lee

Inventor： Min-Suk Lee ,  Sung-Kwon Lee

IPC: H01L21/4763 ,  H01L21/425 ,  H01L21/302 ,  H01L21/461

CPC classification number: H01L21/76897

Abstract: A method for fabricating a semiconductor device is capable of preventing a hard mask layer of a conductive structure from being damaged during a self-aligned contact etching process. The method includes the steps of: forming a plurality of conductive structures including a conductive layer and a hard mask layer on a substrate; sequentially forming a first nitride layer, an oxide layer, a second nitride layer, and an etch stop layer on the plurality of conductive structures; forming an inter-layer insulation layer on the etch stop layer; and performing a self-aligned contact (SAC) etching process selectively etching the inter-layer insulation layer, the etch stop layer, the second nitride layer and the oxide layer until the SAC etching process is stopped at the first nitride layer to thereby form a contact hole exposing the first nitride layer.

Abstract translation: 一种制造半导体器件的方法能够防止导电结构的硬掩模层在自对准接触蚀刻工艺期间被损坏。 该方法包括以下步骤：在衬底上形成包括导电层和硬掩模层的多个导电结构; 在所述多个导电结构上依次形成第一氮化物层，氧化物层，第二氮化物层和蚀刻停止层; 在所述蚀刻停止层上形成层间绝缘层; 以及执行自对准接触（SAC）蚀刻工艺，选择性地蚀刻层间绝缘层，蚀刻停止层，第二氮化物层和氧化物层，直到在第一氮化物层处停止SAC蚀刻工艺，从而形成 露出第一氮化物层的接触孔。

公开(公告)号：US20070015356A1

公开(公告)日：2007-01-18

申请号：US11361525

申请日：2006-02-24

Applicant: Min-Suk Lee ,  Sung-Kwon Lee

Inventor： Min-Suk Lee ,  Sung-Kwon Lee

IPC: H01L21/4763

CPC classification number: H01L21/76802 ,  H01L2221/1057

Abstract: A method for forming a contact hole in a semiconductor device is provided. A method for forming a contact hole in a semiconductor device includes: forming an insulation layer over a bottom structure; forming a hard mask pattern over the insulation layer; etching a portion of the insulation layer using the hard mask pattern as an etch mask to form an opening; forming spacers over sidewalls of the hard mask pattern and the insulation layer patterned by the etching; etching a remaining portion of the insulation layer to form a contact hole exposing a portion of the bottom structure; and removing the spacers and the hard mask pattern.

Abstract translation: 提供了一种在半导体器件中形成接触孔的方法。 在半导体器件中形成接触孔的方法包括：在底部结构上形成绝缘层; 在绝缘层上形成硬掩模图案; 使用硬掩模图案作为蚀刻掩模蚀刻绝缘层的一部分以形成开口; 在硬掩模图案的侧壁和通过蚀刻图案化的绝缘层上形成间隔物; 蚀刻绝缘层的剩余部分以形成暴露底部结构的一部分的接触孔; 并且去除间隔物和硬掩模图案。

公开(公告)号：US07119015B2

公开(公告)日：2006-10-10

申请号：US10879220

申请日：2004-06-30

Applicant: Hyung Soon Park ,  Min Suk Lee ,  Sang Ick Lee ,  Hyun Chul Sohn

Inventor： Hyung Soon Park ,  Min Suk Lee ,  Sang Ick Lee ,  Hyun Chul Sohn

IPC: H01L21/44

CPC classification number: H01L21/76897 ,  H01L21/7684

Abstract: Disclosed is a method for forming a polysilicon plug of a semiconductor device. The method comprises the steps of: forming a stacked pattern of a wordline and a hard mask film on a semiconductor substrate comprising a cell region and a peripheral circuit region; forming a spacer on a sidewall of the stacked pattern; forming an interlayer insulating film on the semiconductor substrate; polishing the interlayer insulating film via a CMP process using the hard mask film as a polishing barrier film; forming a barrier film on the semiconductor substrate including the interlayer insulating film; selectively etching the barrier film and the interlayer insulating film to form a landing plug contact hole; depositing a polysilicon film filling the landing plug contact hole on the semiconductor substrate; blanket-etching the polysilicon film using the barrier film as an etching barrier film; and polishing the polysilicon film and the barrier film using the hard mask film as a polishing barrier film to form a polysilicon plug.

Abstract translation: 公开了一种用于形成半导体器件的多晶硅插塞的方法。 该方法包括以下步骤：在包括单元区域和外围电路区域的半导体衬底上形成字线和硬掩模膜的堆叠图案; 在所述堆叠图案的侧壁上形成间隔物; 在半导体衬底上形成层间绝缘膜; 通过使用硬掩模膜作为抛光阻挡膜的CMP工艺来研磨层间绝缘膜; 在包括层间绝缘膜的半导体衬底上形成阻挡膜; 选择性地蚀刻阻挡膜和层间绝缘膜以形成着陆塞接触孔; 在所述半导体衬底上沉积填充所述着地插头接触孔的多晶硅膜; 使用阻挡膜作为蚀刻阻挡膜对多晶硅膜进行绝缘蚀刻; 并使用硬掩模膜作为抛光阻挡膜研磨多晶硅膜和阻挡膜以形成多晶硅插塞。