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135 条记录 (耗时 0.039 秒)

    Catalyst for electrochemical reduction of oxygen
    61.
    发明申请
    Catalyst for electrochemical reduction of oxygen 有权
    用于电化学还原氧的催化剂

    公开(公告)号：US20080202923A1

    公开(公告)日：2008-08-28

    申请号：US12070832

    申请日：2008-02-21

    申请人： Andrea F. Gulla ,  Robert J. Allen

    发明人： Andrea F. Gulla ,  Robert J. Allen

    IPC分类号： C25B11/08 ,  B01J21/18 ,  B01J23/46

    CPC分类号： C25B11/04 ,  C25B1/26 ,  H01M4/8605 ,  H01M4/923 ,  H01M4/926 ,  Y02P20/129 ,  Y02P20/20

    摘要： The invention relates to a sulphide catalyst for electrochemical reduction of oxygen particularly stable in chemically aggressive environments such as chlorinated hydrochloric acid. The catalyst of the invention comprises a noble metal sulphide single crystalline phase supported on a conductive carbon essentially free of zerovalent metal and of metal oxide phases, obtainable by reduction of metal precursor salts and thio-precursors with a borohydride or other strong reducing agent.

    摘要翻译： 本发明涉及用于电化学还原氧化物的硫化物催化剂，其在化学腐蚀性环境如氯化盐酸中尤其稳定。 本发明的催化剂包含负载在基本上不含零价金属和金属氧化物相的导电碳上的贵金属硫化物单晶相，可通过用硼氢化物或其它强还原剂还原金属前体盐和硫代前体而获得。

    Method and device for aligning a receiving envelope in a mail inserter
    62.
    发明授权
    Method and device for aligning a receiving envelope in a mail inserter 有权
    用于对准邮件插入器中的接收信封的方法和装置

    公开(公告)号：US07398635B2

    公开(公告)日：2008-07-15

    申请号：US11329468

    申请日：2006-01-11

    申请人： James A. Fairweather ,  George J. Doutney ,  Robert J. Allen ,  Thomas M. Lyga ,  Daniel P. Goslicki, Jr.

    发明人： James A. Fairweather ,  George J. Doutney ,  Robert J. Allen ,  Thomas M. Lyga ,  Daniel P. Goslicki, Jr.

    IPC分类号： B65B43/26

    CPC分类号： B43M3/045

    摘要： In a mail inserter having an envelope movement mechanism to move an envelope into an insertion station and a feeder to move a pack of insert material into an insertion position so that the insert material can be inserted into the envelope, a linear array of optical sensing elements is used to determine the position of one edge of the insert material and another linear array of optical sensing elements is used to determine the position of one edge of the receiving envelope in order to make sure that there is sufficient end clearance between the insert material and the receiving envelope. A stepper motor is used to adjust the envelope position, if the end clearance is outside a predetermined range.

    摘要翻译： 在具有包络移动机构以将信封移动到插入台中的邮件插入器和用于将一批插入材料移动到插入位置的馈送器中，使得插入材料可插入外壳中，光学传感元件的线性阵列 用于确定插入材料的一个边缘的位置，并且使用光学感测元件的另一个线性阵列来确定接收包络的一个边缘的位置，以便确保插入材料和插入材料之间存在足够的端部间隙 接收信封。 如果端部间隙超出预定范围，则使用步进电机来调节包络位置。

    IC Layout Optimization To Improve Yield
    63.
    发明申请
    IC Layout Optimization To Improve Yield 失效
    IC布局优化提高产量

    公开(公告)号：US20070294648A1

    公开(公告)日：2007-12-20

    申请号：US11424922

    申请日：2006-06-19

    申请人： Robert J. Allen ,  Faye D. Baker ,  Albert M. Chu ,  Michael S. Gray ,  Jason Hibbeler ,  Daniel N. Maynard ,  Mervyn Y. Tan ,  Robert F. Walker

    发明人： Robert J. Allen ,  Faye D. Baker ,  Albert M. Chu ,  Michael S. Gray ,  Jason Hibbeler ,  Daniel N. Maynard ,  Mervyn Y. Tan ,  Robert F. Walker

    IPC分类号： G06F17/50

    CPC分类号： G06F17/5068

    摘要： A method of and service for optimizing an integrated circuit design to improve manufacturing yield. The invention uses manufacturing data and algorithms to identify areas with high probability of failures, i.e. critical areas. The invention further changes the layout of the circuit design to reduce critical area thereby reducing the probability of a fault occurring during manufacturing. Methods of identifying critical area include common run, geometry mapping, and Voronoi diagrams. Optimization includes but is not limited to incremental movement and adjustment of shape dimensions until optimization objectives are achieved and critical area is reduced.

    摘要翻译： 一种用于优化集成电路设计以提高制造产量的方法和服务。 本发明使用制造数据和算法来识别故障概率高的区域，即关键区域。 本发明进一步改变电路设计的布局以减少临界面积，从而降低在制造过程中发生故障的可能性。 确定关键区域的方法包括通用运行，几何映射和Voronoi图。 优化包括但不限于形状尺寸的增量移动和调整，直到达到优化目标并减小关键面积。

    Sample probability of fault function determination using critical defect size map
    64.
    发明授权
    Sample probability of fault function determination using critical defect size map 失效
    使用关键缺陷尺寸图的故障函数确定的样本概率

    公开(公告)号：US07310788B2

    公开(公告)日：2007-12-18

    申请号：US10906549

    申请日：2005-02-24

    申请人： Robert J. Allen ,  Mervyn Y. Tan

    发明人： Robert J. Allen ,  Mervyn Y. Tan

    IPC分类号： G06F17/50 ,  G06F17/10

    CPC分类号： G06F17/504

    摘要： Methods, systems and program products for determining a probability of fault (POF) function using critical defect size maps. Methods for an exact or a sample POF function are provided. Critical area determinations can also be supplied based on the exact or sample POF functions. The invention provides a less computationally complex and storage-intensive methodology.

    摘要翻译： 使用关键缺陷尺寸图确定故障概率（POF）功能的方法，系统和程序产品。 提供精确或样本POF功能的方法。 也可以根据POF功能的准确或取样来提供关键区域测定。 本发明提供了较少的计算复杂性和存储密集型方法。

    Critical area computation of composite fault mechanisms using voronoi diagrams
    67.
    发明授权
    Critical area computation of composite fault mechanisms using voronoi diagrams 有权
    使用voronoi图的复合故障机制的关键区域计算

    公开(公告)号：US07143371B2

    公开(公告)日：2006-11-28

    申请号：US10709293

    申请日：2004-04-27

    申请人： Robert J. Allen ,  Evanthia Papadopoulou ,  Mervyn Yee-Min Tan

    发明人： Robert J. Allen ,  Evanthia Papadopoulou ,  Mervyn Yee-Min Tan

    IPC分类号： G06F17/50

    CPC分类号： G06F17/5068

    摘要： Disclosed is a method that determines critical areas associated with different types of fault mechanisms in an integrated circuit design. The invention does this by constructing individual Voronoi diagrams for critical areas of individual fault mechanisms and a composite Voronoi diagram based on the individual Voronoi diagrams. The invention computes the critical area for composite fault mechanisms of the integrated circuit design based on the composite Voronoi diagram.

    摘要翻译： 公开了一种在集成电路设计中确定与不同类型的故障机制相关联的关键区域的方法。 本发明通过为单个故障机制的关键区域构建单独的Voronoi图和基于各个Voronoi图的复合Voronoi图来实现。 本发明基于复合Voronoi图计算了集成电路设计复合故障机理的关键区域。

    Integrated circuit macro placing system and method
    68.
    发明授权
    Integrated circuit macro placing system and method 失效
    集成电路宏放置系统及方法

    公开(公告)号：US07124387B2

    公开(公告)日：2006-10-17

    申请号：US10710701

    申请日：2004-07-29

    申请人： Robert J. Allen ,  Steven G. Lovejoy ,  Kevin W. McCullen

    发明人： Robert J. Allen ,  Steven G. Lovejoy ,  Kevin W. McCullen

    IPC分类号： G06F17/50

    CPC分类号： G06F17/5072

    摘要： A method (300) of placing a to-be-placed integrated circuit macro (404) adjacent one or more already-placed macros (400) aboard an integrated circuit chip (100). The method includes the step of performing a canonical ordering of the edges of the to-be-placed and already placed macros. Then, an edge constraint vector (500, 526) is generated for each active edge (668) of the already-placed macro(s) and each edge of the to-be-placed macro. Each of the edge constraint vectors of the to-be-placed macro is compared to each edge constraint vector of the active edge(s) using a string matching algorithm so as to determine whether any edges of the to-be-placed macro are compatible with any active edges of the already-placed macro(s). The method may be implemented in a CAD system (600).

    摘要翻译： 将放置在集成电路芯片（100）上的一个或多个已经放置的宏（400）的待放置集成电路宏（404）放置的方法（300）。 该方法包括执行要放置的和已经放置的宏的边缘的规范排序的步骤。 然后，为已经放置的宏和待放置宏的每个边缘的每个活动边缘（668）生成边缘约束向量（500,526）。 使用字符串匹配算法将待放置的宏的每个边缘约束向量与活动边缘的每个边缘约束向量进行比较，以便确定要被放置的宏的任何边缘是否兼容 具有已放置宏的任何活动边。 该方法可以在CAD系统（600）中实现。

    Method for improving chip yields in the presence of via flaring
    70.
    发明授权
    Method for improving chip yields in the presence of via flaring 失效
    在存在通孔燃烧的情况下提高芯片产量的方法

    公开(公告)号：US06904575B2

    公开(公告)日：2005-06-07

    申请号：US10064098

    申请日：2002-06-11

    申请人： Robert J. Allen ,  Gustavo E. Tellez

    发明人： Robert J. Allen ,  Gustavo E. Tellez

    IPC分类号： G06F17/50

    CPC分类号： G06F17/5081

    摘要： The current invention provides a modification procedure that reduces errors in integrated circuits due to via shorts while at the same time avoiding the unnesting of the layout design and thereby permitting verification of the layout design by LVS testing tools. The current invention identifies if potentially shorting vias have electrically redundant paths and, if so, creates cloned cells of the original cell but void of the potentially shorting vias. The cloned cell is electrically comparable to the original cell. In addition, each instantiation of the original cell in the shapes data base is replaced with the cloned cell when electrical redundancy is present. Also, the number of vias removed can be minimized or maximized while, at the same time, all via electrical shorts are removed, depending on the design requirements.

    摘要翻译： 本发明提供了一种修改过程，该过程减少了集成电路由于通路短路而产生的错误，同时避免了布局设计的不明显，从而允许LVS测试工具对布局设计的验证。 本发明鉴定潜在短路通孔是否具有电冗余路径，如果是，则产生原始单元的克隆单元，但没有潜在的短路通孔。 克隆的细胞与原始细胞电可比较。 此外，当存在电冗余时，形状数据库中的原始单元的每个实例化被克隆单元替换。 此外，取决于设计要求，可以将去除的通路的数量最小化或最大化，同时全部通过电气短路被去除。