公开(公告)号：US10541677B2

公开(公告)日：2020-01-21

申请号：US16156246

申请日：2018-10-10

Applicant: STMicroelectronics, Inc.

Inventor： Pavan Nallamothu

IPC: H03K3/00 ,  H03K3/012 ,  G05F1/575 ,  H03K17/687

Abstract: A voltage generator circuit uses a feedback loop to regulate an output voltage at an output node. A pair of opposite conductivity source-follower transistors are coupled to the output node. A first one of the source-follower transistors operates to provide a fast current transient for charging a capacitive load that is switchably connected to the output node. A second one of the source-follower transistor operate under feedback control to regulate the voltage level at the output node.

公开(公告)号：US10531051B2

公开(公告)日：2020-01-07

申请号：US15978908

申请日：2018-05-14

Applicant: STMicroelectronics, Inc.

Inventor： Oleg Logvinov ,  James D. Allen

IPC: H04N7/18 ,  H04N5/232

Abstract: Embodiments of the present disclosure include a system and a method of accessing a system. An embodiment is a system including an imaging system including a controller and a first camera, the controller having a communication connection configured to transmit or receive content or control signals, and a mobile device including a second camera, the mobile device having a communication interface configured to transmit or receive content or control signals with the controller, the controller being configured to compare images from the first and second cameras to allow access to the controller from the mobile device.

公开(公告)号：US10459243B2

公开(公告)日：2019-10-29

申请号：US15927387

申请日：2018-03-21

Applicant: STMicroelectronics, Inc.

Inventor： Chih-Hung Tai ,  Felix Kim ,  Mark A. Lysinger

IPC: G02B27/64

Abstract: Various embodiments provide an optical image stabilization circuit that synchronizes its gyroscope and drive circuit using gyroscope data ready signals and gyroscope reset signals. In response to a gyroscope data ready signal, the optical image stabilization circuit synchronously obtains position measurements of a camera lens when power drive signals are not transitioning from one power level to another power level, and synchronously transitions the power drive signals simultaneously with gyroscope reset signals. By synchronizing the gyroscope and the drive circuit, the gyroscope and other onboard sensing circuits are isolated from noise generated by the drive circuit.

公开(公告)号：US10438856B2

公开(公告)日：2019-10-08

申请号：US13856325

申请日：2013-04-03

Applicant: STMicroelectronics, Inc.

Inventor： John H. Zhang ,  Chengyu Niu ,  Heng Yang

IPC: H01L21/70 ,  H01L21/8238 ,  H01L29/423 ,  H01L29/49 ,  H01L21/28 ,  H01L29/78 ,  H01L21/285 ,  H01L29/417 ,  H01L29/66 ,  H01L27/092

Abstract: Methods and devices for enhancing mobility of charge carriers. An integrated circuit may include semiconductor devices of two types. The first type of device may include a metallic gate and a channel strained in a first manner. The second type of device may include a metallic gate and a channel strained in a second manner. The gates may include, collectively, three or fewer metallic materials. The gates may share a same metallic material. A method of forming the semiconductor devices on an integrated circuit may include depositing first and second metallic layers in first and second regions of the integrated circuit corresponding to the first and second gates, respectively.

公开(公告)号：US10431682B2

公开(公告)日：2019-10-01

申请号：US15693952

申请日：2017-09-01

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION ,  GLOBALFOUNDRIES, INC. ,  STMicroelectronics, Inc.

Inventor： Qing Liu ,  Ruilong Xie ,  Chun-chen Yeh

IPC: H01L29/78 ,  H01L29/66 ,  H01L21/306 ,  H01L21/02 ,  H01L21/324 ,  H01L29/417

Abstract: A method of fabricating features of a vertical transistor include performing a first etch process to form a first portion of a fin in a substrate; depositing a spacer material on sidewalls of the first portion of the fin; performing a second etch process using the spacer material as a pattern to elongate the fin and form a second portion of the fin in the substrate, the second portion having a width that is greater than the first portion; oxidizing a region of the second portion of the fin beneath the spacer material to form an oxidized channel region; and removing the oxidized channel region to form a vacuum channel.

公开(公告)号：US20190272155A1

公开(公告)日：2019-09-05

申请号：US16281040

申请日：2019-02-20

Applicant: STMicroelectronics, Inc. ,  STMicroelectronics Design and Application S.R.O

Inventor： Mahesh Chowdhary ,  Miroslav Batek ,  Marian Louda

IPC: G06F8/34 ,  G06F8/35 ,  G06F8/36 ,  G06F8/61 ,  H04L29/08 ,  G06F9/451

Abstract: The disclosure describes methods and apparatus for quickly prototyping of a solution developed using one or more sensing devices (e.g., sensors), functional blocks, algorithm libraries, and customized logic. The methods produce firmware executable by a processor (e.g., a microcontroller) on an embedded device such as a development board, expansion board, or the like. By performing these methods on the apparatus described, a user is able to create a function prototype without having deep knowledge of the particular sensing device or any particular programing language. Prototypes developed as described herein enable the user to rapidly test ideas and develop sensing device proofs-of-concept. The solutions produced by the methods and apparatus improve the functioning of the sensor being prototyped and the operation of the embedded device where the sensor is integrated.

公开(公告)号：US20190259673A1

公开(公告)日：2019-08-22

申请号：US16399808

申请日：2019-04-30

Applicant: STMicroelectronics, Inc.

Inventor： Qing Liu ,  John H. Zhang

IPC: H01L21/84 ,  H01L29/66 ,  H01L29/161 ,  H01L29/423 ,  H01L29/06 ,  H01L29/10 ,  H01L21/266 ,  H01L27/12 ,  H01L27/02 ,  H01L21/308 ,  H01L21/265

Abstract: An analog integrated circuit is disclosed in which short channel transistors are stacked on top of long channel transistors, vertically separated by an insulating layer. With such a design, it is possible to produce a high density, high power, and high performance analog integrated circuit chip including both short and long channel devices that are spaced far enough apart from one another to avoid crosstalk. In one embodiment, the transistors are FinFETs and the long channel devices are multi-gate FinFETs. In one embodiment, single and dual damascene devices are combined in a multi-layer integrated circuit cell. The cell may contain various combinations and configurations of the short and long-channel devices. A high density cell can be made by simply shrinking the dimensions of the cells and replicating two or more cells in the same size footprint as the original cell.

公开(公告)号：US10388659B2

公开(公告)日：2019-08-20

申请号：US15939108

申请日：2018-03-28

Applicant: STMicroelectronics, Inc.

Inventor： John H. Zhang

IPC: H01L21/00 ,  H01L21/8238 ,  H01L27/108 ,  H01L29/06 ,  H01L29/16 ,  H01L29/78 ,  H01L29/20 ,  H01L29/66 ,  H01L21/28 ,  H01L27/092 ,  H01L29/423 ,  H01L29/786 ,  H01L29/10 ,  B82Y10/00 ,  H01L29/775 ,  H01L27/08 ,  H01L31/0392 ,  H01L33/04 ,  H01L45/00 ,  H01L29/739 ,  H01L29/49

Abstract: A vertical tunneling FET (TFET) provides low-power, high-speed switching performance for transistors having critical dimensions below 7 nm. The vertical TFET uses a gate-all-around (GAA) device architecture having a cylindrical structure that extends above the surface of a doped well formed in a silicon substrate. The cylindrical structure includes a lower drain region, a channel, and an upper source region, which are grown epitaxially from the doped well. The channel is made of intrinsic silicon, while the source and drain regions are doped in-situ. An annular gate surrounds the channel, capacitively controlling current flow through the channel from all sides. The source is electrically accessible via a front side contact, while the drain is accessed via a backside contact that provides low contact resistance and also serves as a heat sink. Reliability of vertical TFET integrated circuits is enhanced by coupling the vertical TFETs to electrostatic discharge (ESD) diodes.

公开(公告)号：US10388639B2

公开(公告)日：2019-08-20

申请号：US15802525

申请日：2017-11-03

Applicant: International Business Machines Corporation ,  STMicroelectronics, Inc.

Inventor： Lawrence A. Clevenger ,  Carl J. Radens ,  Yiheng Xu ,  John H. Zhang

IPC: H01L21/44 ,  H01L21/48 ,  H01L25/18 ,  H01L25/065 ,  H01L23/31 ,  H01L23/498 ,  H01L25/00 ,  H01L23/13 ,  H01L23/15 ,  H01L23/538

Abstract: Self-aligned three dimensional vertically stacked chip stacks and processes for forming the same generally include two or more vertically stacked chips supported by a scaffolding structure, the scaffolding structure defined by a first scaffolding trench and at least one additional scaffolding trench, the first scaffolding trench comprising a bottom surface having a width and a sidewall having a height extending from the bottom surface to define a lowermost trench in a scaffolding layer, the at least one additional scaffolding trench overlaying the first scaffolding trench having a sidewall having a height and a width, wherein the width of the at least one scaffolding trench is greater than the first scaffolding trench width to define a first stair between the first scaffolding trench and the at least one additional trench; a first chip secured to the first scaffolding trench having a height less than the first scaffolding trench sidewall height; and at least one additional chip secured to and supported by the first stair, wherein the at least one additional chip is vertically spaced apart from the first chip.

公开(公告)号：US20190217612A1

公开(公告)日：2019-07-18

申请号：US16357100

申请日：2019-03-18

Applicant: STMICROELECTRONICS, INC. ,  STMICROELECTRONICS INTERNATIONAL N.V. ,  STMICROELECTRONICS S.R.L.

Inventor： Simon DODD ,  David S. HUNT ,  Joseph Edward SCHEFFELIN ,  Dana GRUENBACHER ,  Stefan H. HOLLINGER ,  Uwe SCHOBER ,  Peter JANOUCH

IPC: B41J2/14 ,  B41J2/175

CPC classification number: B41J2/1433 ,  B41J2/14072 ,  B41J2/14201 ,  B41J2/1753 ,  B41J2/17553 ,  B41J2002/14362 ,  B41J2002/14491

Abstract: The present disclosure provides supports for microfluidic die that allow for nozzles of the microfluidic die to be on a different plane or face a different direction from electrical contacts on the same support. This includes a rigid support having electrical contacts on a different side of the rigid support with respect to a direction of ejection of the nozzles, and a semi-flexible support or semi-rigid support that allow the electrical contacts to be moved with respect to a direction of ejection of the nozzles. The semi-flexible and semi-rigid supports allow the die to be up to and beyond a 90 degree angle with respect to a plane of the electrical contacts. The different supports allow for a variety of positions of the microfluidic die with respect to a position of the electrical contacts.