公开(公告)号：US12164002B2

公开(公告)日：2024-12-10

申请号：US18066783

申请日：2022-12-15

Applicant: STMicroelectronics International N.V.

Inventor： John Kevin Moore ,  Gavin Stuart Ball

IPC: G01R31/317 ,  G04F10/00

Abstract: A time-to-digital converter (TDC) circuit with self-testing function includes: a D flip-flop, where an input terminal of the D flip-flop is configured to be coupled to a data signal, and a clock terminal of the D flip-flop is configured to be coupled to a clock signal; and an AND gate, where a first input terminal of the AND gate is configured to be coupled to an enable signal of the TDC circuit, a second input terminal of the AND gate is configured to be coupled to a test signal, and an output terminal of the AND gate is coupled to a control terminal of the D flip-flop.

公开(公告)号：US20240405798A1

公开(公告)日：2024-12-05

申请号：US18651120

申请日：2024-04-30

Applicant: STMICROELECTRONICS INTERNATIONAL N.V.

Inventor： Riccardo CONDORELLI ,  Antonino MONDELLO ,  Michele Alessandro CARRANO ,  Salvatore COSTA ,  Michele BOTTARO ,  Pascal FABRE ,  Philippe BOLLARD ,  Felice Alberto TORRISI

IPC: H04B1/7183 ,  H04L7/033

Abstract: Method of operating a radio communication system during a stand-by time interval in a stand-by state. The method comprises: applying clock division processing to a reference clock signal and producing a divided clock signal; applying PLL processing to the divided clock signal producing a PLL clock signal; receiving at least one input signal; when the input signal has a first logic value, interrupting applying PLL processing to the divided clock signal and enabling counting clock signal edges of the divided clock signal; when said counting clock signal edges reaches a first target count value, restarting applying PLL processing; continuing counting clock signal edges until reaching a second target count value; when said counting reaches the second target count value, issuing and sampling an end-count signal based on the PLL clock signal, producing a timing clock signal as a result and providing the timing clock signal to a user circuit.

公开(公告)号：US20240405670A1

公开(公告)日：2024-12-05

申请号：US18203299

申请日：2023-05-30

Applicant: STMicroelectronics International N.V.

Inventor： Yannick HAGUE ,  Romain LAUNOIS ,  Guillaume THIENNOT

IPC: H02M1/42 ,  H02M1/00 ,  H02M1/08

Abstract: A bidirectional PFC system includes a high-frequency branch with a first transistor connected between an IO node and a high-frequency tap, and a second transistor connected between the high-frequency tap and a reference node, and a low-frequency branch with a first thyristor connected between the IO node and a low-frequency tap, and a second thyristor connected between the low-frequency tap and the reference node. An inductor is connected between the first node and the high-frequency tap. A first capacitor is connected between the first node and the low-frequency tap. The first node and the low-frequency tap are coupled to input terminals. A control circuit generates first and second gate drive signals for the transistors so as to modify an AC signal at the input terminals such that the AC current falls below a holding current of the second thyristor prior to zero crossing of the AC voltage.

公开(公告)号：US20240404596A1

公开(公告)日：2024-12-05

申请号：US18676719

申请日：2024-05-29

Applicant: STMicroelectronics International N.V.

Inventor： Antonino CONTE ,  Francesco LA ROSA

IPC: G11C13/00

Abstract: First, second input terminals of a sense amplifier are coupled to first, second memory sensing nodes. A first input transistor has a channel arranged between a first comparator input and a first comparator output, and a control terminal at a bias node. A second input transistor has a channel arranged between a second comparator input and a second comparator output, and a control terminal at a bias node. The first and second comparator inputs are selectively couplable to each other, in response to compensation signal assertion, or to the first and second input terminals, in response to compensation signal de-assertion. The bias node is selectively couplable to a comparator biasing node in response to bias enable assertion, or is floating in response to the bias enable de-assertion. A sensing circuit produces a read signal as a function of a difference between first, second currents at the comparator outputs.

公开(公告)号：US20240403602A1

公开(公告)日：2024-12-05

申请号：US18204069

申请日：2023-05-31

Applicant: STMicroelectronics International N.V.

Inventor： Tommaso MILANESE ,  Edoardo Charbon ,  Brent Hearn

IPC: G06N3/0442 ,  G06F17/16

Abstract: Systems, apparatuses, methods, and computer programming products for machine learning with a LSTM accelerator are provided. The LSTM accelerator may comprise a finite state machine (FSM) configured with a plurality of states comprising a machine learning algorithm; a weight memory configured to at least store a plurality of weights and a plurality of biases; one or more activation registers; a hidden state memory; and a plurality of processing elements. The LSTM accelerator may apply the machine learning algorithm of the FSM by performing a plurality of operations with the plurality of processing elements including one or more matrix-vector multiplication operations, vector-vector multiplication operations, vector-vector addition operations, and non-linear activation operations.

公开(公告)号：US20240402249A1

公开(公告)日：2024-12-05

申请号：US18203345

申请日：2023-05-30

Applicant: STMicroelectronics International N.V.

Inventor： Venkata Narayanan Srinivasan ,  Manish Sharma ,  Jeena Mary George ,  Umesh Chandra Srivastava

IPC: G01R31/3185

Abstract: According to an embodiment, a method for testing a triple-voting flop (TVF) is provided. The method includes providing a first and a second scan enable signal by a control circuit to, respectively, a first scan flip-flop and a third scan flip-flop of the TVF; receiving a third scan enable signal at the second scan flip-flop of the TVF; providing a scan input signal to the first scan flip-flop, the second scan flip-flop, and the third scan flip-flop; controlling the first scan enable signal, the second scan enable signal, and the third scan enable signal; receiving, at an output of the TVF, a scan output signal; and determining whether the TVF suffers from a fault based on the scan output signal and the controlling of the first scan enable signal, the second scan enable signal, and the third scan enable signal.

公开(公告)号：US12160237B2

公开(公告)日：2024-12-03

申请号：US17843693

申请日：2022-06-17

Applicant: STMicroelectronics International N.V.

Inventor： Kailash Kumar ,  Ravinder Kumar

IPC: H03K19/0185 ,  H03K19/003

Abstract: An integrated circuit includes an output pad, and I/O driver that drives data to the output pad, and a predriver that controls the I/O driver. The integrated circuit includes maximum voltage generator that receives a first supply voltage and a second supply voltage and outputs to the predriver a maximum voltage corresponding to the higher of the first supply voltage and the second supply voltage.

公开(公告)号：US20240395924A1

公开(公告)日：2024-11-28

申请号：US18662577

申请日：2024-05-13

Applicant: STMicroelectronics International N.V.

Inventor： Salvatore CASCINO ,  Mario Giuseppe SAGGIO ,  Mario PULVIRENTI

IPC: H01L29/78 ,  H01L29/10 ,  H01L29/16 ,  H01L29/66

Abstract: An electronic device includes a semiconductor body of SiC having an upper surface and a lower surface opposite to each other along a first axis and including: a drain substrate extending into the semiconductor body starting from the bottom surface and with a first electrical conductivity type; a drift layer extending into the semiconductor body starting from the upper surface and with the first electrical conductivity type and a second dopant concentration; a body region accommodated in the drift layer; and a source region accommodated in the body region. The electronic device further includes a gate structure on the upper surface. The semiconductor body further comprises at least one doped pocket region which is buried in the drift layer, has a second electrical conductivity type and is aligned along the first axis with the source region and/or with the gate structure.

公开(公告)号：US20240395319A1

公开(公告)日：2024-11-28

申请号：US18791901

申请日：2024-08-01

Applicant: STMicroelectronics International N.V.

Inventor： Harsh RAWAT ,  Kedar Janardan DHORI ,  Promod KUMAR ,  Nitin CHAWLA ,  Manuj AYODHYAWASI

IPC: G11C11/418

Abstract: SRAM cells are connected in columns by bit lines and connected in rows by first and second word lines coupled to first and second data storage sides of the SRAM cells. First the first word lines are actuated in parallel and then next the second word lines are actuated in parallel in first and second phases, respectively, of an in-memory compute operation. Bit line voltages in the first and second phases are processed to generate an in-memory compute operation decision. A low supply node reference voltage for the SRAM cells is selectively modulated between a ground voltage and a negative voltage. The first data storage side receives the negative voltage and the second data storage side receives the ground voltage during the second phase. Conversely, the second data storage side receives the negative voltage and the first data storage side receives the ground voltage during the first phase.

公开(公告)号：US20240393439A1

公开(公告)日：2024-11-28

申请号：US18671527

申请日：2024-05-22

Applicant: STMicroelectronics International N.V.

Inventor： Raul Andres BIANCHI ,  Christel Marie-Noëlle BUJ

IPC: G01S7/481 ,  G01S17/894 ,  H01L27/146

Abstract: The present disclosure relates to a process to control an optoelectronic device comprising a single-photon avalanche diode n a substrate, wherein the diode comprises a first region doped with a first type of conductivity level with a first face of the substrate and a second region doped with a second type of conductivity extending from the first face to a second face of the substrate opposed to the first face, wherein the device comprises a third conducting or semiconducting region at the second face, wherein the process comprises the application of a biasing voltage to the third region in order to generate an electric field that accelerates the charges generated in the diode.