公开(公告)号：US5482881A

公开(公告)日：1996-01-09

申请号：US403460

申请日：1995-03-14

申请人： Jian Chen ,  Yuan Tang ,  Scott Luning ,  Salvatore F. Cagnina

发明人： Jian Chen ,  Yuan Tang ,  Scott Luning ,  Salvatore F. Cagnina

IPC分类号： H01L21/8247 ,  H01L27/115

CPC分类号： H01L27/11521 ,  H01L27/115

摘要： A flash EEPROM having reduced column leakage current suitably includes cells with more uniform erase times arranged in an array. An intermediate n+ implant immediately following the DDI implant step suitably provides an enhanced doping profile in the tunneling region, which increases the rate at which F-N tunneling occurs to erase the cells, and which increases the uniformity of F-N tunneling rates among memory cells within the array. A thermal cycle drives the intermediate n+ implant deeper into the tunneling region. Alternatively, an n+ implant may be performed at a relatively large angle with respect to the semiconductor substrate, which improves the doping concentration in the tunneling region of the source.

摘要翻译： 具有降低的列泄漏电流的快闪EEPROM适当地包括以阵列布置的更均匀擦除次数的单元。 紧接在DDI注入步骤之后的中间n +注入适当地提供隧道区域中的增强的掺杂分布，这增加了发生FN隧道以擦除单元的速率，并且这增加阵列内的存储单元之间的FN隧穿速率的均匀性 。 热循环驱动中间n +植入物更深入隧道区域。 或者，可以相对于半导体衬底以相对大的角度执行n +注入，这改善了源极的隧道区域中的掺杂浓度。

公开(公告)号：US08404592B2

公开(公告)日：2013-03-26

申请号：US12509918

申请日：2009-07-27

申请人： Scott Luning ,  Frank S. Johnson

发明人： Scott Luning ,  Frank S. Johnson

IPC分类号： H01L21/302

CPC分类号： H01L21/3086 ,  H01L21/845 ,  H01L29/66795

摘要： Methods for fabricating semiconductor structures, such as fin structures of FinFET transistors, are provided. In one embodiment, a method comprises providing a semiconductor substrate and forming a plurality of mandrels overlying the semiconductor substrate. Each of the mandrels has sidewalls. L-shaped spacers are formed about the sidewalls of the mandrels. Each L-shaped spacer comprises a rectangular portion disposed at a base of a mandrel and an orthogonal portion extending from the rectangular portion. Each L-shaped spacer also has a spacer width. The orthogonal portions are removed from each of the L-shaped spacers leaving at least a portion of the rectangular portions. The semiconductor substrate is etched to form fin structures, each fin structure having a width substantially equal to the spacer width.

摘要翻译： 提供了制造半导体结构的方法，例如FinFET晶体管的鳍结构。 在一个实施例中，一种方法包括提供半导体衬底并形成覆盖半导体衬底的多个心轴。 每个心轴都有侧壁。 围绕心轴的侧壁形成L形间隔物。 每个L形间隔件包括设置在心轴的基部和从矩形部分延伸的正交部分的矩形部分。 每个L形间隔物也具有间隔物宽度。 从每个L形间隔件中取出正交部分，留下矩形部分的至少一部分。 蚀刻半导体衬底以形成鳍结构，每个鳍结构的宽度基本上等于间隔物宽度。

公开(公告)号：US20110266622A1

公开(公告)日：2011-11-03

申请号：US13180300

申请日：2011-07-11

申请人： Scott Luning ,  Frank Scott Johnson

发明人： Scott Luning ,  Frank Scott Johnson

IPC分类号： H01L29/786

CPC分类号： H01L29/7842 ,  H01L29/66795 ,  H01L29/785

摘要： A method of fabricating a semiconductor device is provided. The method forms a fin arrangement on a semiconductor substrate, the fin arrangement comprising one or more semiconductor fin structures. The method continues by forming a gate arrangement overlying the fin arrangement, where the gate arrangement includes one or more adjacent gate structures. The method proceeds by forming an outer spacer around sidewalls of each gate structure. The fin arrangement is then selectively etched, using the gate structure and the outer spacer(s) as an etch mask, resulting in one or more semiconductor fin sections underlying the gate structure(s). The method continues by forming a stress/strain inducing material adjacent sidewalls of the one or more semiconductor fin sections.

摘要翻译： 提供一种制造半导体器件的方法。 所述方法在半导体衬底上形成翅片布置，所述翅片布置包括一个或多个半导体翅片结构。 该方法通过形成覆盖鳍片布置的栅极布置继续，其中栅极布置包括一个或多个相邻栅极结构。 该方法通过在每个栅极结构的侧壁周围形成外部间隔来进行。 然后使用栅极结构和外部间隔物作为蚀刻掩模来选择性地蚀刻鳍片布置，从而导致栅极结构下面的一个或多个半导体鳍片部分。 该方法通过在一个或多个半导体鳍片部分的侧壁附近形成应力/应变诱导材料来继续。

公开(公告)号：US20110027978A1

公开(公告)日：2011-02-03

申请号：US12512814

申请日：2009-07-30

申请人： Michael J. HARGROVE ,  Frank Scott JOHNSON ,  Scott LUNING

发明人： Michael J. HARGROVE ,  Frank Scott JOHNSON ,  Scott LUNING

IPC分类号： H01L21/26 ,  H01L21/28

CPC分类号： H01L21/26586 ,  H01L29/66795 ,  H01L29/66803 ,  H01L29/7847 ,  H01L29/785

摘要： Embodiments of a method are provided for fabricating a non-planar semiconductor device including a substrate having a plurality of raised crystalline structures formed thereon. In one embodiment, the method includes the steps of amorphorizing a portion of each raised crystalline structure included within the plurality of raised crystalline structures, forming a sacrificial strain layer over the plurality of raised crystalline structures to apply stress to the amorphized portion of each raised crystalline structure, annealing the non-planar semiconductor device to recrystallize the amorphized portion of each raised crystalline structure in a stress-memorized state, and removing the sacrificial strain layer.

摘要翻译： 提供了一种用于制造包括其上形成有多个凸起的晶体结构的基板的非平面半导体器件的方法的实施例。 在一个实施方案中，该方法包括以下步骤：将包含在多个凸起的晶体结构内的每个凸起的晶体结构的一部分非晶化，在多个凸起的晶体结构上形成牺牲应变层，以将应力施加到每个凸起晶体的非晶化部分 结构，退火所述非平面半导体器件以使应力存储状态下的每个凸起晶体结构的非晶化部分重结晶，以及去除所述牺牲应变层。

公开(公告)号：US20110024841A1

公开(公告)日：2011-02-03

申请号：US12904662

申请日：2010-10-14

申请人： Frank Bin YANG ,  Andrew M. WAITE ,  Scott LUNING

发明人： Frank Bin YANG ,  Andrew M. WAITE ,  Scott LUNING

IPC分类号： H01L29/78 ,  H01L25/07

CPC分类号： H01L21/26586 ,  H01L29/66659 ,  H01L29/7834 ,  H01L2924/0002 ,  Y10S438/931 ,  H01L2924/00

摘要： A method for fabricating a MOSFET (e.g., a PMOS FET) includes providing a semiconductor substrate having surface characterized by a (110) surface orientation or (110) sidewall surfaces, forming a gate structure on the surface, and forming a source extension and a drain extension in the semiconductor substrate asymmetrically positioned with respect to the gate structure. An ion implantation process is performed at a non-zero tilt angle. At least one spacer and the gate electrode mask a portion of the surface during the ion implantation process such that the source extension and drain extension are asymmetrically positioned with respect to the gate structure by an asymmetry measure.

摘要翻译： 一种用于制造MOSFET（例如，PMOS FET）的方法包括提供具有由（110）表面取向或（110）侧壁表面表征的表面的半导体衬底，在表面上形成栅极结构，并形成源延伸和 半导体衬底中的漏极延伸部相对于栅极结构非对称地定位。 以非零倾角进行离子注入工艺。 在离子注入过程期间，至少一个间隔物和栅电极掩盖表面的一部分，使得源极延伸和漏极延伸通过不对称度量相对于栅极结构不对称地定位。

公开(公告)号：US20100308381A1

公开(公告)日：2010-12-09

申请号：US12480269

申请日：2009-06-08

申请人： Scott LUNING ,  Frank S. JOHNSON ,  Michael J. HARGROVE

发明人： Scott LUNING ,  Frank S. JOHNSON ,  Michael J. HARGROVE

IPC分类号： H01L29/78 ,  H01L21/22 ,  H01L21/336

CPC分类号： H01L29/7843 ,  H01L21/845 ,  H01L27/1211 ,  H01L29/66795 ,  H01L29/785

摘要： Methods for fabricating FinFET structures with stress-inducing source/drain-forming spacers and FinFET structures having such spacers are provided herein. In one embodiment, a method for fabricating a FinFET structure comprises fabricating a plurality of parallel fins overlying a semiconductor substrate. Each of the fins has sidewalls. A gate structure is fabricated overlying a portion of each of the fins. The gate structure has sidewalls and overlies channels within the fins. Stress-inducing sidewall spacers are formed about the sidewalls of the fins and the sidewalls of the gate structure. The stress-inducing sidewall spacers induce a stress within the channels. First conductivity-determining ions are implanted into the fins using the stress-inducing sidewall spacers and the gate structure as an implantation mask to form source and drain regions within the fins.

摘要翻译： 本文提供了制造具有应力诱导源极/漏极形成间隔物的FinFET结构和具有这种间隔物的FinFET结构的方法。 在一个实施例中，制造FinFET结构的方法包括制造覆盖半导体衬底的多个平行散热片。 每个翅片都有侧壁。 制造覆盖每个翅片的一部分的栅极结构。 栅极结构在翅片内具有侧壁并覆盖通道。 应力诱导侧壁间隔件围绕翅片的侧壁和栅极结构的侧壁形成。 应力诱导侧壁间隔物在通道内引起应力。 使用应力诱导侧壁间隔物和栅极结构作为注入掩模将第一导电率确定离子注入到鳍中，以在翅片内形成源区和漏区。

公开(公告)号：US20080079033A1

公开(公告)日：2008-04-03

申请号：US11536126

申请日：2006-09-28

申请人： Andrew M. Waite ,  Scott Luning

发明人： Andrew M. Waite ,  Scott Luning

IPC分类号： H01L29/78 ,  H01L21/336

CPC分类号： H01L29/6656 ,  H01L21/823807 ,  H01L21/823814 ,  H01L29/6653 ,  H01L29/66636 ,  H01L29/7848

摘要： A stressed field effect transistor and methods for its fabrication are provided. The field effect transistor comprises a silicon substrate with a gate insulator overlying the silicon substrate. A gate electrode overlies the gate insulator and defines a channel region in the silicon substrate underlying the gate electrode. A first silicon germanium region having a first thickness is embedded in the silicon substrate and contacts the channel region. A second silicon germanium region having a second thickness greater than the first thickness and spaced apart from the channel region is also embedded in the silicon substrate.

摘要翻译： 提供了一种应力场效应晶体管及其制造方法。 场效应晶体管包括具有覆盖硅衬底的栅极绝缘体的硅衬底。 栅电极覆盖栅极绝缘体，并且在栅电极下面的硅衬底中限定沟道区。 具有第一厚度的第一硅锗区域嵌入在硅衬底中并与沟道区域接触。 具有大于第一厚度并且与沟道区间隔开的第二厚度的第二硅锗区域也嵌入在硅衬底中。

公开(公告)号：US20080006876A1

公开(公告)日：2008-01-10

申请号：US11456326

申请日：2006-07-10

申请人： Yun-Yu Wang ,  Linda Black ,  Judson R. Holt ,  Woo-Hyeong Lee ,  Scott Luning ,  Christopher D. Sheraw

发明人： Yun-Yu Wang ,  Linda Black ,  Judson R. Holt ,  Woo-Hyeong Lee ,  Scott Luning ,  Christopher D. Sheraw

IPC分类号： H01L27/12 ,  H01L27/01 ,  H01L31/0392

CPC分类号： H01L21/02639 ,  H01L21/02381 ,  H01L21/02433 ,  H01L21/02532 ,  H01L21/02609 ,  H01L21/84

摘要： Methods and a structure are disclosed for providing stacking fault reduced epitaxially grown silicon for use in hybrid surface orientation structures. In one embodiment, a method includes depositing a silicon nitride liner over a silicon oxide liner in an opening, etching to remove the silicon oxide liner and silicon nitride liner on a lower surface of the opening, undercutting the silicon nitride liner adjacent to the lower surface, and epitaxially growing silicon in the opening. The silicon is substantially reduced of stacking faults because of the negative slope created by the undercut.

摘要翻译： 公开了用于提供用于混合表面取向结构的堆垛层错缺陷外延生长的硅的方法和结构。 在一个实施例中，一种方法包括在开口中的氧化硅衬垫上沉积氮化硅衬垫，蚀刻以除去开口的下表面上的氧化硅衬垫和氮化硅衬垫，将邻近下表面的氮化硅衬垫 并且在开口中外延生长硅。 由于底切产生的负斜率，硅片堆积层错误大大减少。

公开(公告)号：US20060281271A1

公开(公告)日：2006-12-14

申请号：US11150899

申请日：2005-06-13

申请人： David Brown ,  William En ,  Thorsten Kammler ,  Paul Besser ,  Scott Luning

发明人： David Brown ,  William En ,  Thorsten Kammler ,  Paul Besser ,  Scott Luning

IPC分类号： H01L21/336

CPC分类号： H01L29/6653 ,  H01L29/665 ,  H01L29/6656 ,  H01L29/66628 ,  H01L29/7834

摘要： Integration schemes are presented which provide for decoupling the placement of deep source/drain (S/D) implants with respect to a selective epitaxial growth (SEG) raised S/D region, as well as decoupling silicide placement relative to a raised S/D feature. These integration schemes may be combined in multiple ways to permit independent control of the placement of these features for optimizing device performance. The methodology utilizes multiple spacers to decrease current crowding effects in devices due to proximity effects between LDD and deep S/D regions in reduced architecture devices.

摘要翻译： 提出了集成方案，其提供了相对于选择性外延生长（SEG）引起的S / D区域去耦合深源/漏（S / D）植入物的放置以及相对于升高的S / D去耦硅化物放置 特征。 这些集成方案可以以多种方式组合，以允许独立控制这些特征的放置以优化装置性能。 该方法利用多个间隔物来减少由于减少的架构设备中LDD与深S / D区域之间的邻近效应而导致的器件中的电流拥挤效应。

公开(公告)号：US20060223250A1

公开(公告)日：2006-10-05

申请号：US11280484

申请日：2005-11-16

申请人： Karla Romero ,  Thorsten Kammler ,  Scott Luning ,  Hans Van Meer

发明人： Karla Romero ,  Thorsten Kammler ,  Scott Luning ,  Hans Van Meer

IPC分类号： H01L21/302 ,  H01L21/8234 ,  H01L21/31

CPC分类号： H01L21/32139 ,  H01L21/823814 ,  H01L29/6656 ,  H01L29/66628 ,  H01L29/7834

摘要： By providing a hard mask layer stack including at least three different layers for patterning a gate electrode structure, constraints demanded by sophisticated lithography, as well as cap layer integrity, in a subsequent selective epitaxial growth process may be accomplished, thereby providing the potential for further device scaling of transistor devices requiring raised drain and source regions.

摘要翻译： 通过提供包括用于图案化栅电极结构的至少三个不同层的硬掩模层堆叠，可以实现随后的选择性外延生长工艺中复杂光刻所需的约束以及覆盖层完整性，从而提供进一步的潜力 晶体管器件的器件缩放需要高的漏极和源极区域。