公开(公告)号：US5982697A

公开(公告)日：1999-11-09

申请号：US045608

申请日：1998-03-20

Applicant: Brett Williams ,  Scott Schaefer

Inventor： Brett Williams ,  Scott Schaefer

IPC: G11C7/10 ,  G11C11/4072 ,  G11C8/00

CPC classification number: G11C11/4072 ,  G11C7/1045 ,  G11C7/1072

Abstract: A method for initially programming a synchronous dynamic random access memory (SDRAM) device to have a first control operating option in response to a first command and for reprogramming the SDRAM device to have a second control operating option in response to a second command.

Abstract translation: 一种用于最初编程同步动态随机存取存储器（SDRAM）装置的方法，用于响应于第一命令具有第一控制操作选项，并且用于重新编程SDRAM装置以响应于第二命令具有第二控制操作选项。

公开(公告)号：US5717639A

公开(公告)日：1998-02-10

申请号：US783380

申请日：1997-01-13

Applicant: Brett Williams ,  Scott Schaefer

Inventor： Brett Williams ,  Scott Schaefer

IPC: G11C5/06 ,  G11C7/10 ,  G11C11/4072 ,  G11C11/4096 ,  G11C7/00

CPC classification number: G11C5/066 ,  G11C11/4072 ,  G11C11/4096 ,  G11C7/1042 ,  G11C7/1045 ,  G11C7/1072

Abstract: A synchronous dynamic random access memory (SDRAM) device having a master control circuit for accepting a first command and a second command and having an initialization and reprogramming circuit. The master control circuit generates an initialization signal in response to the first command and generates a reprogramming signal in response to the second command. The initialization and reprogramming circuit responds to the initialization signal to control initial programming of a control operation feature and responds to the reprogramming signal to control a reprogramming of the control operation feature.

公开(公告)号：US5457659A

公开(公告)日：1995-10-10

申请号：US276993

申请日：1994-07-19

Applicant: Scott Schaefer

Inventor： Scott Schaefer

IPC: G11C11/401 ,  G11C7/10 ,  G11C11/406 ,  G11C7/00

CPC classification number: G11C7/1024 ,  G11C11/406

Abstract: A DRAM which adapted to provide extended data output upon the input of appropriate logic signals is provided. The DRAM includes a CAS before RAS (CBR) detection circuit that controls the data output during a CBR refresh cycle. The operation of the CBR detection circuit is dependent on the state of the output enable (OE) signal during a CBR refresh cycle (e.g., WE-high, CAS-low, RAS-high then low while CAS low). If OE is low, then the CBR detection circuit will trigger a first output mode for the data out buffer (e.g., normal fast page output mode in a non-persistent version and the programmed mode in a persistent version) along with a refresh pulse to the refresh controller. If OE is high then the CBR detection circuit will trigger an extended data output from the data out buffer.

Abstract translation: 提供一种适于在输入适当逻辑信号时提供扩展数据输出的DRAM。 DRAM包括在CBR刷新周期期间控制数据输出的＆upbar＆C＆amp;前＆amp;＆nbspB＆R（CBR）检测电路。 CBR检测电路的操作取决于CBR刷新周期期间输出使能（＆upbar＆O）信号的状态（例如，＆upbar＆W-high，＆upbar＆C-low，＆upbar＆R-high then low，upbar＆C low） 。 如果＆upbar＆O为低电平，则CBR检测电路将触发数据输出缓冲区的第一个输出模式（例如，非持久版本中的正常快速输出模式和持久版本中的编程模式）以及刷新脉冲 到刷新控制器。 如果＆upbar＆O为高电平，则CBR检测电路将触发从数据输出缓冲区的扩展数据输出。

公开(公告)号：US07404071B2

公开(公告)日：2008-07-22

申请号：US10816239

申请日：2004-04-01

Applicant: Jeffery W. Janzen ,  Scott Schaefer ,  Todd D. Farrell

Inventor： Jeffery W. Janzen ,  Scott Schaefer ,  Todd D. Farrell

IPC: G06F9/312 ,  G06F15/177

CPC classification number: G06F11/3037 ,  G06F11/073 ,  G06F11/0751 ,  G06F11/3058

Abstract: Memory modules having accurate operating current values stored thereon and methods for fabricating and implementing such devices to improve system performance. Memory modules comprising a number of volatile memory devices may be fabricated. Operating current values for specific memory devices on the memory module or a specific lot in which the memory devices are fabricated may be stored on a non-volatile memory device on the memory module. A system may be configured in accordance with the operating current values stored on the non-volatile memory device such that operating current thresholds are not exceeded.

Abstract translation: 具有存储在其上的精确工作电流值的存储器模块以及用于制造和实施这些装置以改善系统性能的方法。 可以制造包括多个易失性存储器件的存储器模块。 存储器模块或其中制造存储器件的特定批量的特定存储器件的操作电流值可以存储在存储器模块上的非易失性存储器件上。 可以根据存储在非易失性存储器件上的工作电流值来配置系统，使得不超过工作电流阈值。

公开(公告)号：US07330382B2

公开(公告)日：2008-02-12

申请号：US10929282

申请日：2004-08-30

Applicant: Scott Schaefer

Inventor： Scott Schaefer

IPC: G11C7/00

CPC classification number: G11C7/1066 ,  G11C7/1045 ,  G11C7/1051 ,  G11C7/22 ,  G11C7/222 ,  G11C11/4076 ,  G11C11/4096

Abstract: A method and apparatus for programming a data strobe (DQS) preamble in a memory by loading a defined set of bits into one or more registers of the memory, where one or more bits are formatted specifically for enabling the data strobe preamble. At least one of the bits is used to enable a data strobe preamble as either a default data strobe preamble of the memory or as a reduced data strobe preamble with a time length set equal to a fraction of the default preamble or a fraction of a clock cycle. The enabling bit can be used to provide a input for generating a delay that provides a delayed signal to drivers of the memory for producing a reduced data strobe preamble and for sequencing or driving data to be read out of the memory. The reduced data strobe preamble can also be used for writing data into the memory.

Abstract translation: 一种用于通过将定义的一组位加载到存储器的一个或多个寄存器中来对存储器中的数据选通（DQS）前导码进行编程的方法和装置，其中一个或多个位被格式化以用于启用数据选通前导码。 这些位中的至少一个用于使数据选通前同步码作为存储器的默认数据选通前导码，或者作为缩减数据选通前导，其时间长度设置为等于默认前导码的一部分或时钟的一部分 周期。 使能位可以用于提供用于产生延迟的输入，该延迟向存储器的驱动器提供延迟的信号，用于产生减少的数据选通前导码，并用于排序或驱动要从存储器读出的数据。 缩减数据选通前导码也可用于将数据写入存储器。

公开(公告)号：US20060149996A1

公开(公告)日：2006-07-06

申请号：US11338200

申请日：2006-01-24

Applicant: Jeffery Janzen ,  Scott Schaefer ,  Todd Farrell

Inventor： Jeffery Janzen ,  Scott Schaefer ,  Todd Farrell

IPC: G06F11/00

CPC classification number: G11C11/4074 ,  G11C5/00 ,  G11C5/143 ,  G11C7/04 ,  G11C16/20 ,  G11C29/02 ,  G11C29/028 ,  G11C2029/4402 ,  G11C2029/5006

Abstract: Methods of manufacturing memory devices and memory modules comprising memory device. Specifically, respective operating current values may be measured and/or stored on a plurality of memory devices. More specifically, the operating current values may be stored in programmable elements, such as antifuses, on memory devices. The memory devices may be coupled to a substrate to form a memory module. A non-volatile memory device may be coupled to the substrate. The operating current values may be read from the programmable elements and stored in the non-volatile memory device. Once the memory module is incorporated into a system, the programmable elements or non-volatile memory may be accessed such that the system can be configured to optimally operate in accordance with the operating current values measured for each memory device in the system.

Abstract translation: 制造存储器件和包括存储器件的存储器模块的方法。 具体地，可以在多个存储器件上测量和/或存储各自的工作电流值。 更具体地，工作电流值可以存储在存储器件上的诸如反熔丝的可编程元件中。 存储器件可以耦合到衬底以形成存储器模块。 非易失性存储器件可以耦合到衬底。 可以从可编程元件读取工作电流值并存储在非易失性存储器件中。 一旦将存储器模块并入到系统中，可以访问可编程元件或非易失性存储器，使得可以将系统配置为根据对系统中的每个存储器件测量的工作电流值进行最佳操作。

公开(公告)号：US20060007760A1

公开(公告)日：2006-01-12

申请号：US11216489

申请日：2005-08-31

Applicant: Scott Schaefer

Inventor： Scott Schaefer

IPC: G11C7/00

CPC classification number: G11C7/1066 ,  G11C7/1045 ,  G11C7/1051 ,  G11C7/22 ,  G11C7/222 ,  G11C11/4076 ,  G11C11/4096

Abstract: A method and apparatus for programming a data strobe (DQS) preamble in a memory by loading a defined set of bits into one or more registers of the memory, where one or more bits are formatted specifically for enabling the data strobe preamble. At least one of the bits is used to enable a data strobe preamble as either a default data strobe preamble of the memory or as a reduced data strobe preamble with a time length set equal to a fraction of the default preamble or a fraction of a clock cycle. The enabling bit can be used to provide a input for generating a delay that provides a delayed signal to drivers of the memory for producing a reduced data strobe preamble and for sequencing or driving data to be read out of the memory. The reduced data strobe preamble can also be used for writing data into the memory.

Abstract translation: 一种用于通过将定义的一组位加载到存储器的一个或多个寄存器中来对存储器中的数据选通（DQS）前导码进行编程的方法和装置，其中一个或多个位被格式化以用于启用数据选通前导码。 这些位中的至少一个用于使数据选通前同步码作为存储器的默认数据选通前导码，或者作为缩减数据选通前导，其时间长度设置为等于默认前导码的一部分或时钟的一部分 周期。 使能位可以用于提供用于产生延迟的输入，该延迟向存储器的驱动器提供延迟的信号，用于产生减少的数据选通前导码，并用于排序或驱动要从存储器读出的数据。 缩减数据选通前导码也可用于将数据写入存储器。

公开(公告)号：US20050249013A1

公开(公告)日：2005-11-10

申请号：US10816424

申请日：2004-04-01

Applicant: Jeffery Janzen ,  Scott Schaefer ,  Todd Farrell

Inventor： Jeffery Janzen ,  Scott Schaefer ,  Todd Farrell

IPC: G06F12/00 ,  G11C5/00 ,  G11C11/4074 ,  G11C16/20 ,  G11C29/02

CPC classification number: G11C11/4074 ,  G11C5/00 ,  G11C5/143 ,  G11C7/04 ,  G11C16/20 ,  G11C29/02 ,  G11C29/028 ,  G11C2029/4402 ,  G11C2029/5006

Abstract: A technique for storing accurate operating current values using programmable elements on memory devices. More specifically, programmable elements, such as antifuses, located on a memory device are programmed with measured operating current values corresponding to the memory device, during fabrication. The memory device may be incorporated into a memory module that is incorporated into a system. Once the memory module is incorporated into a system, the programmable elements may be accessed such that the system can be configured to optimally operate in accordance with the operating current values measured for each memory device in the system.

Abstract translation: 一种使用可编程元件在存储器件上存储精确的工作电流值的技术。 更具体地，在制造期间，位于存储器件上的诸如反熔丝的可编程元件被编程为对应于存储器件的测量的工作电流值。 存储器件可以并入到并入到系统中的存储器模块中。 一旦将存储器模块并入到系统中，可以访问可编程元件，使得系统可以被配置为根据对系统中的每个存储器件测量的工作电流值进行最佳操作。

公开(公告)号：US06359801B1

公开(公告)日：2002-03-19

申请号：US09652226

申请日：2000-08-29

Applicant: Scott Schaefer

Inventor： Scott Schaefer

IPC: G11C502

CPC classification number: G11C7/22 ,  G11C8/12

Abstract: A method for accessing a memory array for an electronic device comprises a design which requires fewer memory devices to be activated to access a plurality of data bits, thereby reducing the amount of power required to access the data bits. The design comprises the use of a plurality of memory devices, each of which has a plurality of arrays and data out lines.

Abstract translation: 用于访问用于电子设备的存储器阵列的方法包括需要更少的存储器件被激活以访问多个数据位的设计，从而减少访问数据位所需的功率量。 该设计包括使用多个存储器件，每个存储器件具有多个阵列和数据输出线。

公开(公告)号：US5912860A

公开(公告)日：1999-06-15

申请号：US926940

申请日：1997-09-10

Applicant: Scott Schaefer

Inventor： Scott Schaefer

IPC: G11C7/10 ,  G11C8/00 ,  G11C8/06 ,  G11C11/408

CPC classification number: G11C7/22 ,  G11C11/4076 ,  G11C11/4082 ,  G11C11/4087 ,  G11C7/1018 ,  G11C7/1027 ,  G11C7/1072 ,  G11C8/06 ,  G11C8/10 ,  G11C8/18

Abstract: Disclosed is a synchronous DRAM memory module with control circuitry that allows the memory module to operate partially asynchronously. Specifically, a circuit is disclosed which utilizes address transition detection to begin decoding the column-address immediately after a new column-address is present on the address bus lines and without waiting for the column-address strobe signal to synchronize with the rising or falling edge of the synchronizing clock signal. Also disclosed is a manner of controlling the latching circuitry whereby each new column-address may be decoded and held within a buffer until the column-address strobe signal notifies the circuitry that the column-address is correct and is to be input into the microprocessor. Thus, each new column-address will be decoded immediately after it is present on the address lines and undesired column-addresses will be discarded, while desired column-addresses are input into the memory array bank immediately upon the presence of the column-address strobe which denotes that the column-address is final. The present invention improves the access times of read and write operations in synchronous DRAM memory by up to a complete clock cycle.