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    TEMPORAL ALIGNMENT OF CODEC DATA WITH WIRELESS LOCAL AREA NETWORK RF SLOTS
    61.
    发明申请
    TEMPORAL ALIGNMENT OF CODEC DATA WITH WIRELESS LOCAL AREA NETWORK RF SLOTS 有权
    使用无线局域网射频单元进行CODEC数据的时间对齐

    公开(公告)号：US20070291723A1

    公开(公告)日：2007-12-20

    申请号：US11845928

    申请日：2007-08-28

    申请人： Vivian Chou ,  Charles Aragones ,  Sherman Lee

    发明人： Vivian Chou ,  Charles Aragones ,  Sherman Lee

    IPC分类号： H04Q7/24

    CPC分类号： H04W88/06 ,  H04W84/12

    摘要： A wireless local area network (WLAN) transceiving integrated circuit services voice communications in a WLAN with at least one other WLAN device. The WLAN transceiving integrated circuit includes a WLAN interface, an input buffer, a transcoder, and a processor. The WLAN interface wirelessly communicates with the at least one WLAN device to receive packetized audio data from the at least one WLAN device. The input buffer operably couples to the WLAN interface and receives the packetized audio data from the WLAN interface. The transcoder converts the packetized audio data to Pulse Code Modulated (PCM) audio data and outputs the PCM audio data to a coupled audio COder/DECoder (CODEC) such that the PCM audio data is substantially temporally aligned with Radio Frequency (RF) slots of the WLAN interface.

    摘要翻译： 无线局域网（WLAN）收发集成电路在具有至少一个其它WLAN设备的WLAN中进行语音通信服务。 WLAN收发集成电路包括WLAN接口，输入缓冲器，代码转换器和处理器。 WLAN接口与至少一个WLAN设备无线地通信，以从至少一个WLAN设备接收分组化的音频数据。 输入缓冲器可操作地耦合到WLAN接口并从WLAN接口接收分组化的音频数据。 代码转换器将打包的音频数据转换为脉冲编码调制（PCM）音频数据，并将PCM音频数据输出到耦合的音频编解码器（CODEC），使得PCM音频数据基本上在时间上对齐于射频（RF） WLAN接口。

    Temporal alignment of codec data with wireless local area network RF slots
    62.
    发明授权
    Temporal alignment of codec data with wireless local area network RF slots 有权
    编解码器数据与无线局域网RF时隙的时间对齐

    公开(公告)号：US07277420B2

    公开(公告)日：2007-10-02

    申请号：US10293452

    申请日：2002-11-13

    申请人： Vivian Chou ,  Charles Aragones ,  Sherman Lee

    发明人： Vivian Chou ,  Charles Aragones ,  Sherman Lee

    IPC分类号： H04J3/06

    CPC分类号： H04W88/06 ,  H04W84/12

    摘要： A wireless local area network (WLAN) transceiving integrated circuit services voice communications in a WLAN with at least one other WLAN device. The WLAN transceiving integrated circuit includes a WLAN interface, an input buffer, a transcoder, and a processor. The WLAN interface wirelessly communicates with the at least one WLAN device to receive packetized audio data from the at least one WLAN device. The input buffer operably couples to the WLAN interface and receives the packetized audio data from the WLAN interface. The transcoder operably couples to the input buffer and receives the packetized audio data from the input buffer. The transcoder converts the packetized audio data to Pulse Code Modulated (PCM) audio data and outputs the PCM audio data to a coupled audio COder/DECoder (CODEC). The processor operably couples to the WLAN interface, the input buffer, and the transcoder. The transcoder outputs the PCM audio data to the audio CODEC such that the PCM audio data is substantially temporally aligned with Radio Frequency (RF) slots of the WLAN interface.

    摘要翻译： 无线局域网（WLAN）收发集成电路在具有至少一个其它WLAN设备的WLAN中进行语音通信服务。 WLAN收发集成电路包括WLAN接口，输入缓冲器，代码转换器和处理器。 WLAN接口与至少一个WLAN设备无线地通信，以从至少一个WLAN设备接收分组化的音频数据。 输入缓冲器可操作地耦合到WLAN接口并从WLAN接口接收分组化的音频数据。 代码转换器可操作地耦合到输入缓冲器并从输入缓冲器接收分组化音频数据。 代码转换器将打包的音频数据转换为脉冲编码调制（PCM）音频数据，并将PCM音频数据输出到耦合的音频编解码器（CODEC）。 处理器可操作地耦合到WLAN接口，输入缓冲器和代码转换器。 代码转换器将PCM音频数据输出到音频CODEC，使得PCM音频数据基本上在时间上与WLAN接口的射频（RF）时隙对准。

    Wireless data communications using FIFO for synchronization memory
    63.
    发明授权
    Wireless data communications using FIFO for synchronization memory 有权
    无线数据通信使用FIFO进行同步存储

    公开(公告)号：US07228392B2

    公开(公告)日：2007-06-05

    申请号：US10413689

    申请日：2003-04-15

    申请人： Sherman Lee ,  Vivian Y. Chou ,  John H. Lin

    发明人： Sherman Lee ,  Vivian Y. Chou ,  John H. Lin

    IPC分类号： G06F12/02

    CPC分类号： G06F9/328 ,  G06F8/66 ,  G06F9/268 ,  H04B1/7156 ,  H04B2001/71566 ,  H04J3/062 ,  H04L25/05 ,  H04W84/18 ,  H04W88/02

    摘要： A microprocessor system architecture is disclosed which allows for the selective execution of programmed ROM microcode or, alternatively, RAM microcode if there has been a correction or update made to the ROM microcode originally programmed into the system. Patched or updated RAM microcode is utilized or executed only to the extent of changes to the ROM microcode, otherwise the ROM microcode is executed in its normal fashion. When a patch is received, it is loaded into system RAM along with instructions or other appropriate signals to direct the execution of the patched or updated microcode from RAM instead of the existing ROM microcode. Various methods are presented for selecting the execution of the appropriate microcode depending upon whether there have been changes made to it.

    摘要翻译： 公开了一种微处理器系统架构，其允许选择性地执行编程的ROM微代码，或者替代地，如果已经对最初编程到系统中的ROM微代码进行了校正或更新，则可以选择性地执行RAM微代码。 修补或更新的RAM微代码仅在ROM微代码的改变程度上被使用或执行，否则ROM微代码以其正常方式执行。 当接收到补丁时，它将与指令或其他适当的信号一起加载到系统RAM中，以指导来自RAM的修补或更新的微代码的执行，而不是现有的ROM微代码。 呈现各种方法用于根据是否对其进行了改变来选择适当的微代码的执行。

    Method for identifying and correcting error in a central processing unit
    64.
    发明授权
    Method for identifying and correcting error in a central processing unit 有权
    用于识别和纠正中央处理单元中的错误的方法

    公开(公告)号：US06484274B1

    公开(公告)日：2002-11-19

    申请号：US09430522

    申请日：1999-10-29

    申请人： Sherman Lee ,  David G. Kyle

    发明人： Sherman Lee ,  David G. Kyle

    IPC分类号： H02H305

    CPC分类号： G06F11/366 ,  G06F11/3652

    摘要： A central processing unit (CPU) repeatedly interrupts execution of software to save the CPU state, i.e. contents of various storage elements internal to the CPU, until an error occurs during the execution. On occurrence of the error, the CPU once again saves state and only then passes control to a handler in the software for handling the error. The state saving steps can be implemented in a computer process by use of a timer interrupt or by use of system management, or ICE breakpoint instructions that are included in the x86 instruction set. Errors can be debugged off-line in a development system, for example, by use of an in-circuit emulator to load the saved CPU states sequentially into the development system, thereby to recreate the error condition. Errors can also be debugged proactively, even before the error occurs, by use of a number of known-to-be-erroneous instructions and corresponding fix instructions. For proactive debugging, the CPU compares instructions to be executed with each of the known-to-be-erroneous instructions, and on finding a match, injects the corresponding fix instructions into the to-be-executed instructions. Therefore, known errors e.g. the PENTIUM arithmetic bug are avoided, e.g. by replacing one arithmetic instruction with another arithmetic instruction. Moreover, if an error has not yet been debugged, a temporary fix instruction can be used to gracefully terminate an application.

    摘要翻译： 中央处理单元（CPU）重复地中断软件的执行以节省CPU状态，即CPU内部的各种存储元件的内容，直到在执行期间发生错误。 在发生错误时，CPU再次保存状态，然后仅将控件传递到软件中的处理程序以处理错误。 状态保存步骤可以通过使用定时器中断或通过使用系统管理或包含在x86指令集中的ICE断点指令在计算机进程中实现。 可以在开发系统中离线调试错误，例如，通过使用在线仿真器将已保存的CPU状态顺序加载到开发系统中，从而重新创建错误状况。 也可以通过使用一些已知的被错误的指令和相应的修复指令来主动地调试错误，甚至在错误发生之前。 为了主动调试，CPU将要执行的指令与每个已知的要错误的指令进行比较，并且在找到匹配时，将相应的修补指令注入到要执行的指令中。 因此，已知的错误例如 避免了PENTIUM算术错误，例如 通过用另一个算术指令替换一个算术指令。 此外，如果还没有调试错误，则可以使用临时修复指令来正常终止应用程序。

    Port for fine tuning a central processing unit
    65.
    发明授权
    Port for fine tuning a central processing unit 失效
    端口用于微调中央处理单元

    公开(公告)号：US5937203A

    公开(公告)日：1999-08-10

    申请号：US710337

    申请日：1996-09-16

    申请人： Sherman Lee ,  David G. Kyle

    发明人： Sherman Lee ,  David G. Kyle

    IPC分类号： G06F9/318 ,  G06F9/38 ,  G06F11/34 ,  G06F12/08 ,  G06F15/78 ,  G06F9/455

    CPC分类号： G06F9/3867 ,  G06F12/0802 ,  G06F15/7867 ,  G06F9/30036 ,  G06F9/3836 ,  G06F9/3848 ,  G06F9/3855 ,  G06F9/3857 ,  G06F9/3873 ,  G06F9/3897 ,  G06F11/3447 ,  G06F2212/601

    摘要： A central processing unit (hereinafter "CPU") has a number of functional units and a tuning port for modifying one or more parameters of the functional units (hereinafter "tunable units"). The combination (also called a "tuning assembly") formed by a tuning port and the tunable units allows a CPU to be fine tuned, i.e. take on different configuration profiles (as defined by the tunable units' parameters) for efficiently executing different application programs. Therefore, a CPU that includes a tuning assembly as described herein can take on a first configuration profile capable of most efficiently executing a first application program such as a computer game, and can take on a second configuration profile capable of most efficiently executing a second application program such as a spreadsheet and so on. The CPU's configuration profile can be changed even during the execution of an application program by changing the tunable units' parameters. Such fine tuning allows the CPU to execute different portions of an application program more efficiently than possible in the prior art.

    摘要翻译： 中央处理单元（以下称为“CPU”）具有多个功能单元和用于修改功能单元（以下称为“可调单元”）的一个或多个参数的调谐端口。 由调谐端口和可调单元形成的组合（也称为“调谐组件”）允许CPU被微调，即采用不同的配置配置文件（由可调谐单元的参数定义），以有效执行不同的应用程序 。 因此，包括如本文所述的调谐组件的CPU可以承载能够最有效地执行诸如计算机游戏的第一应用程序的第一配置简档，并且可以承载能够最有效地执行第二应用的第二配置简档 程式如电子表格等等。 即使在应用程序执行期间，CPU的配置配置文件也可以通过更改可调谐单元的参数来更改。 这样的微调允许CPU比现有技术更有效地执行应用程序的不同部分。

    Swivel base apparatus and method of making a swivel base
    66.
    发明授权
    Swivel base apparatus and method of making a swivel base 失效
    旋转基座装置及旋转底座的制造方法

    公开(公告)号：US5782451A

    公开(公告)日：1998-07-21

    申请号：US597548

    申请日：1996-02-02

    申请人： Garnett Carnahan ,  Caroline Carnahan ,  Sherman Lee

    发明人： Garnett Carnahan ,  Caroline Carnahan ,  Sherman Lee

    IPC分类号： A47B11/00 ,  A47C3/18 ,  F16M11/08 ,  A47B95/00

    CPC分类号： A47B11/00 ,  A47C3/18 ,  F16M11/08 ,  F16M2200/08

    摘要： An apparatus which includes a swivel base formed of a first plate and a second plate. The first and second plates each have a central aperture which is defined by a hook-shaped section of the second plate which extends over an interior edge of the first plate defining the first plate's central aperture. The hook-shaped section is preferably circumferentially continuous and fixes the first and second plates together while allowing for sliding engagement between the first and second plates. Bearing members, such as circumferentially spaced ball bearings, are provided externally to the hook section and between the plates to facilitate sliding and load distribution. One of the plates includes hollow reception ports for holding the bearing circumferentially in place with respect to that plate while the opposite plate has a continuous riding ring in which the bearings are free to rotate. Each plate has an interior and exterior, preferably horizontal, plate section, and an intermediate section sloping between the adjacent, integral edges of the plate's interior and exterior sections. One manner of assembling the swivel base is described as well as an assembly including two structures to which the exterior sections of the plates are secured. In another embodiment, a swivel base features one or more ribs formed adjacent the elongated fastening holes. The invention also features a rounded edge extending about the entire periphery of a swivel base plate adjacent the fastener slots.

    摘要翻译： 一种装置，包括由第一板和第二板形成的旋转底座。 第一和第二板各自具有中心孔，该中心孔由第二板的钩形部分限定，其在限定第一板的中心孔的第一板的内部边缘上延伸。 钩形部分优选是周向连续的，并且将第一和第二板固定在一起，同时允许第一和第二板之间的滑动接合。 轴承构件，例如周向间隔开的球轴承，设置在钩部分的外部和板之间，以便于滑动和负载分配。 其中一个板包括中空的接收端口，用于将轴承相对于板保持在周向就位，而相对的板具有连续的骑行环，轴承可自由转动。 每个板具有内部和外部，优选水平的板部分，以及在板的内部和外部部分的相邻的整体边缘之间倾斜的中间部分。 描述组装旋转底座的一种方式以及包括两个结构件的组件，板的外部部分固定到该组件上。 在另一个实施例中，旋转底座具有邻近细长紧固孔形成的一个或多个肋。 本发明还具有围绕邻近紧固件槽的旋转底板的整个周边延伸的圆形边缘。

    Method and system for graceful recovery from a fault in peripheral devices using a variety of bus structures
    68.
    发明授权
    Method and system for graceful recovery from a fault in peripheral devices using a variety of bus structures 失效
    使用各种总线结构从外围设备故障中正常恢复的方法和系统

    公开(公告)号：US5712967A

    公开(公告)日：1998-01-27

    申请号：US635843

    申请日：1996-04-22

    申请人： Leonid Grossman ,  Sherman Lee ,  Ramkrishna Vepa

    发明人： Leonid Grossman ,  Sherman Lee ,  Ramkrishna Vepa

    IPC分类号： G06F11/267 ,  G06F11/00

    CPC分类号： G06F11/2221

    摘要： A method and system for resetting a peripheral device which could use a variety of buses have been disclosed. The method and system determine what bus type the peripheral device has. The method and system then automatically execute a reset process capable of resetting the peripheral device having that bus type. A beneficial aspect of this invention is allowing a peripheral device to gracefully recover from a fault. In this aspect, the method detects whether a peripheral device fault has occurred. Where the fault has occurred, the method determines whether any of a plurality of processes executable by the peripheral device is being executed. The processes comprise those processes which could result in significant loss of data, loss of connection to a network, or adversely affect performance if the peripheral device is reset during execution. If none of the processes is being executed, the method automatically resets the peripheral device. The automatic reset process determines the bus type of the peripheral device. The automatic reset process then automatically executes a reset process capable of resetting the peripheral device having that bus type. According to the method and system, a peripheral device which may use a variety of buses can be reset or made to recover from faults without user intervention, without loss of connection to any networks, and with minimal loss of data.

    摘要翻译： 已经公开了用于复位可以使用各种总线的外围设备的方法和系统。 该方法和系统确定外围设备的总线类型。 该方法和系统然后自动执行能够复位具有该总线类型的外围设备的复位处理。 本发明的有益方面是允许外围设备从故障中正常恢复。 在这方面，该方法检测是否发生了外围设备故障。 在发生故障的情况下，该方法确定是否正在执行由外围设备执行的多个进程中的任何一个。 这些过程包括可能导致数据的显着丢失，与网络的连接的丢失，或者如果外围设备在执行期间复位则不利地影响性能的过程。 如果没有执行任何进程，该方法将自动重置外围设备。 自动复位过程确定外围设备的总线类型。 自动复位处理然后自动执行能够复位具有该总线类型的外围设备的复位处理。 根据该方法和系统，可以使用各种总线的外围设备被重新设置或者从故障中恢复而无需用户干预，而不损失与任何网络的连接，并且数据丢失最少。