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    Strain inducing semiconductor regions
    63.
    发明授权
    Strain inducing semiconductor regions 有权
    应变诱导半导体区域

    公开(公告)号：US08530884B2

    公开(公告)日：2013-09-10

    申请号：US13160886

    申请日：2011-06-15

    Applicant: Suman Datta ,  Jack T. Kavalieros ,  Been-Yih Jin

    Inventor： Suman Datta ,  Jack T. Kavalieros ,  Been-Yih Jin

    IPC: H01L29/06 ,  H01L31/072

    CPC classification number: H01L29/1033 ,  H01L29/0673 ,  H01L29/201 ,  H01L29/205 ,  H01L29/41725 ,  H01L29/66431 ,  H01L29/66545 ,  H01L29/66628 ,  H01L29/66636 ,  H01L29/66787 ,  H01L29/775 ,  H01L29/78 ,  H01L29/785

    Abstract: A method to form a strain-inducing semiconductor region is described. In one embodiment, formation of a strain-inducing semiconductor region laterally adjacent to a crystalline substrate results in a uniaxial strain imparted to the crystalline substrate, providing a strained crystalline substrate. In another embodiment, a semiconductor region with a crystalline lattice of one or more species of charge-neutral lattice-forming atoms imparts a strain to a crystalline substrate, wherein the lattice constant of the semiconductor region is different from that of the crystalline substrate, and wherein all species of charge-neutral lattice-forming atoms of the semiconductor region are contained in the crystalline substrate.

    Abstract translation: 描述形成应变诱导半导体区域的方法。 在一个实施方案中，形成横向邻近晶体衬底的应变诱导半导体区域导致赋予晶体衬底的单轴应变，从而提供应变的晶体衬底。 在另一个实施方案中，具有一种或多种电荷 - 中性晶格形成原子的晶格的半导体区域向晶体衬底赋予应变，其中半导体区域的晶格常数与晶体衬底的晶格常数不同，以及 其中所述半导体区域的电荷 - 中性晶格形成原子的所有种类都包含在所述晶体衬底中。

    TFET based 6T SRAM cell
    64.
    发明授权
    TFET based 6T SRAM cell 有权
    基于TFET的6T SRAM单元

    公开(公告)号：US08369134B2

    公开(公告)日：2013-02-05

    申请号：US12912904

    申请日：2010-10-27

    Applicant: Jawar Singh ,  Ramakrishnan Krishnan ,  Saurabh Mookerjea ,  Suman Datta ,  Vijaykrishnan Narayanan

    Inventor： Jawar Singh ,  Ramakrishnan Krishnan ,  Saurabh Mookerjea ,  Suman Datta ,  Vijaykrishnan Narayanan

    IPC: G11C11/00

    CPC classification number: G11C11/412

    Abstract: Memory devices and methods of operation are provided. A memory device includes first and second cross-coupled inverters and first and second access transistors coupled to an input node of the second inverter. The memory device also includes a control circuit for providing a first reference voltage at a first ground node of the first inverter and a second reference voltage at a second ground node of the second inverter. The first access transistor is configured to conduct current from a first bit line to the input node and to provide substantially no current conduction from the input node to the first bit line. The second access transistor is configured to conduct current from the input node to one of the first bit line and a second bit line and to provide substantially no current conduction from the input node to the one of first and second bit lines.

    Abstract translation: 提供了存储器件和操作方法。 存储器件包括第一和第二交叉耦合的反相器以及耦合到第二反相器的输入节点的第一和第二存取晶体管。 存储装置还包括用于在第一反相器的第一接地节点处提供第一参考电压的控制电路和在第二反相器的第二接地节点处的第二参考电压。 第一存取晶体管被配置为将电流从第一位线传导到输入节点，并且基本上不提供从输入节点到第一位线的电流传导。 第二存取晶体管被配置为将电流从输入节点传导到第一位线和第二位线之一，并且基本上不提供从输入节点到第一和第二位线之一的电流传导。

    Method to introduce uniaxial strain in multigate nanoscale transistors by self aligned SI to SIGE conversion processes and structures formed thereby
    66.
    发明授权
    Method to introduce uniaxial strain in multigate nanoscale transistors by self aligned SI to SIGE conversion processes and structures formed thereby 有权
    通过自对准SI将SIGNA转换过程和结构形成的多晶纳米级晶体管中的单轴应变的方法

    公开(公告)号：US08288233B2

    公开(公告)日：2012-10-16

    申请号：US11864726

    申请日：2007-09-28

    Applicant: Been-Yih Jin ,  Brian Doyle ,  Jack Kavalieros ,  Suman Datta

    Inventor： Been-Yih Jin ,  Brian Doyle ,  Jack Kavalieros ,  Suman Datta

    IPC: H01L21/8244

    CPC classification number: H01L29/7851 ,  H01L29/66795 ,  H01L29/7848

    Abstract: Methods of forming a microelectronic structure are described. Embodiments of those methods may include providing a gate electrode comprising a top surface and first and second laterally opposite sidewalls, wherein a hard mask is disposed on the top surface, a source drain region disposed on opposite sides of the gate electrode, and a spacer disposed on the first and second laterally opposed sidewalls of the gate electrode, forming a silicon germanium layer on exposed portions of the top surface and the first and second laterally opposite sidewalls of the source drain region and then oxidizing a portion of the silicon germanium layer, wherein a germanium portion of the silicon germanium layer is forced down into the source drain region to convert a silicon portion of the source drain region into a silicon germanium portion of the source drain region.

    Abstract translation: 描述形成微电子结构的方法。 这些方法的实施例可以包括提供包括顶表面和第一和第二横向相对的侧壁的栅电极，其中硬掩模设置在顶表面上，源极漏极区域设置在栅电极的相对侧上， 在栅电极的第一和第二横向相对的侧壁上，在源漏区的顶表面和第一和第二横向相对的侧壁的暴露部分上形成硅锗层，然后氧化硅锗层的一部分，其中 硅锗层的锗部分被迫下降到源极漏极区域中，以将源极区域的硅部分转换成源极漏极区域的硅锗部分。

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