公开(公告)号：US08120429B1

公开(公告)日：2012-02-21

申请号：US12787722

申请日：2010-05-26

Applicant: Tim Tri Hoang ,  Wilson Wong ,  Kazi Asaduzzaman ,  Simardeep Maangat ,  Sergey Shumarayev ,  Rakesh H. Patel

Inventor： Tim Tri Hoang ,  Wilson Wong ,  Kazi Asaduzzaman ,  Simardeep Maangat ,  Sergey Shumarayev ,  Rakesh H. Patel

IPC: H03L7/00 ,  H03K3/03

CPC classification number: H03L7/0995 ,  H03K3/0322 ,  H03K3/35613 ,  H03K2005/00228 ,  H03K2005/00234

Abstract: Methods and apparatus are provided for generating a clock signal with relatively high bandwidth and relatively low phase noise. A circuit of the invention can include a pair of transistors serially coupled between a signal of relatively high voltage and a source of relatively low voltage, where a voltage of the signal of relatively high voltage can vary according to a voltage of a variable control signal. A gate of one of the pair of transistors can be coupled to an input clock signal, and an output node between the pair of transistors can be coupled to an output clock signal. The circuit can also include a third transistor, whose drain and source are coupled to the output clock signal, and whose gate can be coupled to a gear input signal. This circuit can advantageously operate under at least two different gears, each with different bandwidth and phase noise characteristics.

Abstract translation: 提供了用于产生具有相对较高带宽和相对较低相位噪声的时钟信号的方法和装置。 本发明的电路可以包括串联耦合在相对高电压的信号和相对低电压的源之间的一对晶体管，其中相对高电压的信号的电压可以根据可变控制信号的电压而变化。 一对晶体管中的一个的栅极可以耦合到输入时钟信号，并且该对晶体管之间的输出节点可以耦合到输出时钟信号。 电路还可以包括第三晶体管，其漏极和源极耦合到输出时钟信号，并且其栅极可以耦合到齿轮输入信号。 该电路可以有利地在至少两个不同的齿轮下运行，每个齿轮具有不同的带宽和相位噪声特性。

公开(公告)号：US20110235756A1

公开(公告)日：2011-09-29

申请号：US13151717

申请日：2011-06-02

Applicant: Weiqi Ding ,  Sergey Shumarayev ,  Wilson Wong ,  Thungoc M. Tran ,  Tim Tri Hoang

Inventor： Weiqi Ding ,  Sergey Shumarayev ,  Wilson Wong ,  Thungoc M. Tran ,  Tim Tri Hoang

IPC: H04L27/06

CPC classification number: H04L25/45

Abstract: A loss-of-signal detector includes digital and analog monitoring of incoming data. The incoming signal is compared digitally to at least one predetermined pattern that may indicate a loss of signal, and also is monitored by an analog detector that detects transitions in the data. If the digital comparison fails to match any of the at least one predetermined pattern, or if transitions are detected by the analog monitoring, even if the digital comparison produces a pattern match, then loss of signal is not indicated.

Abstract translation: 信号丢失检测器包括对输入数据进行数字和模拟监测。 输入信号被数字地比较为可以指示信号丢失的至少一个预定模式，并且还由检测数据中的转换的模拟检测器监视。 如果数字比较不能匹配至少一个预定模式中的任何一个，或者如果通过模拟监视检测到转换，即使数字比较产生模式匹配，则不指示信号丢失。

公开(公告)号：US20110188621A1

公开(公告)日：2011-08-04

申请号：US12700433

申请日：2010-02-04

Applicant: Kazi Asaduzzaman ,  Tim Tri Hoang ,  Tin H. Lai ,  Shou-Po Shih ,  Sergey Shumarayev

Inventor： Kazi Asaduzzaman ,  Tim Tri Hoang ,  Tin H. Lai ,  Shou-Po Shih ,  Sergey Shumarayev

IPC: H04L7/00

CPC classification number: H03L7/08 ,  H03L7/0807 ,  H03L7/0814 ,  H03L7/087 ,  H03L7/0898 ,  H03L7/099 ,  H03L7/183 ,  H04L7/0337

Abstract: An integrated circuit (“IC”) may include clock and data recovery (“CDR”) circuitry for recovering data information from an input serial data signal. The CDR circuitry may include a reference clock loop and a data loop. A retimed (recovered) data signal output by the CDR circuitry is monitored by other control circuitry on the IC for a communication change request contained in that signal. Responsive to such a request, the control circuitry can change an operating parameter of the CDR circuitry (e.g., a frequency division factor used in either of the above-mentioned loops). This can help the IC support communication protocols that employ auto-speed negotiation.

Abstract translation: 集成电路（“IC”）可以包括用于从输入串行数据信号恢复数据信息的时钟和数据恢复（“CDR”）电路。 CDR电路可以包括参考时钟环路和数据环路。 由CDR电路输出的重新定时（恢复）数据信号由IC上的其它控制电路监视用于包含在该信号中的通信改变请求。 响应于这种请求，控制电路可以改变CDR电路的操作参数（例如，在上述任何一个循环中使用的分频因子）。 这可以帮助IC支持采用自动速度协商的通信协议。

公开(公告)号：US07903679B1

公开(公告)日：2011-03-08

申请号：US11622396

申请日：2007-01-11

Applicant: Sergey Shumarayev ,  Wilson Wong ,  Thungoc M. Tran ,  Tim Tri Hoang

Inventor： Sergey Shumarayev ,  Wilson Wong ,  Thungoc M. Tran ,  Tim Tri Hoang

IPC: H04L12/56

CPC classification number: H03K19/17744

Abstract: In a programmable logic device with a number of different types of serial interfaces, different power supply filtering schemes are applied to different interfaces. For interfaces operating at the lowest data rates—e.g., 1 Gbps—circuit-board level filtering including one or more decoupling capacitors may be provided. For interfaces operating at somewhat higher data rates—e.g., 3 Gbps—modest on-package filtering also may be provided, which may include power-island decoupling. For interfaces operating at still higher data rates—e.g., 6 Gbps—more substantial on-package filtering, including one or more on-package decoupling capacitors, also may be provided. For interfaces operating at the highest data rates—e.g., 10 Gbps—on-die filtering, which may include one or more on-die filtering or regulating networks, may be provided. The on-die regulators may be programmably bypassable allowing a user to trade off performance for power savings.

Abstract translation: 在具有多种不同类型的串行接口的可编程逻辑器件中，不同的电源滤波方案被应用于不同的接口。 对于以最低数据速率操作的接口，例如，可以提供包括一个或多个去耦电容器的1Gbps电路板电平滤波器。 对于以较高数据速率工作的接口，例如，也可以提供3 Gbps适度的封装内滤波，这可能包括功率岛解耦。 对于以更高的数据速率运行的接口，例如，也可以提供包括一个或多个封装内去耦电容器的6Gbps更实质的封装内滤波。 对于以最高数据速率工作的接口，例如，可以提供10Gbps片上滤波，其可以包括一个或多个片上滤波或调节网络。 片上调节器可以可编程地旁路，允许用户权衡功能以节省功率。

公开(公告)号：US07812659B1

公开(公告)日：2010-10-12

申请号：US11432420

申请日：2006-05-10

Applicant: Sergey Shumarayev ,  Rakesh H Patel ,  William W Bereza ,  Tim Tri Hoang ,  Thungoc Tran

Inventor： Sergey Shumarayev ,  Rakesh H Patel ,  William W Bereza ,  Tim Tri Hoang ,  Thungoc Tran

IPC: G06F1/04 ,  H04L7/00

CPC classification number: H03L7/22 ,  G06F1/06

Abstract: A programmable logic device (“PLD”) or the like has a plurality of data transmitter channels. Certain circuitry is shared by the channels. The shared circuitry includes at least one phase-locked loop (“PLL”) circuit for producing a primary clock signal, and global frequency divider circuitry for producing at least one global secondary clock signal based on the primary signal. The primary and global secondary signal(s) are distributed to the channels. Each of the channels includes local frequency divider circuitry for producing at least one local secondary clock signal based on the primary signal. Each channel also includes selection circuitry for selecting either the global or local secondary signal(s) for use by clock utilization circuitry of the channel. The clock utilization circuitry may include serializer circuitry for converting data from parallel to serial form.

Abstract translation: 可编程逻辑器件（“PLD”）等具有多个数据发送器通道。 某些电路由通道共享。 共享电路包括用于产生主时钟信号的至少一个锁相环（“PLL”）电路和用于基于主信号产生至少一个全局辅助时钟信号的全局分频器电路。 主要和全局辅助信号被分配到信道。 每个通道包括本地分频器电路，用于基于主信号产生至少一个本地辅助时钟信号。 每个通道还包括选择电路，用于选择由信道的时钟利用电路使用的全局或局部辅助信号。 时钟利用电路可以包括用于将数据从并行转换为串行形式的串行化器电路。

公开(公告)号：US07812634B1

公开(公告)日：2010-10-12

申请号：US11726471

申请日：2007-03-21

Applicant: Sergey Shumarayev ,  Thungoc M. Tran ,  Tim Tri Hoang

Inventor： Sergey Shumarayev ,  Thungoc M. Tran ,  Tim Tri Hoang

IPC: H03K19/173

CPC classification number: H03K19/17736 ,  H03K19/1774 ,  H03K19/17744

Abstract: Transceiver circuitry on a programmable logic device integrated circuit (“PLD”) is preferably provided in a plurality of identical or at least similar modules. Each module preferably includes a plurality of transceiver channels and a clock source unit. Clock distribution circuitry is provided for distributing the signal of a module's clock source to all of the transceiver channels in that module, and also selectively beyond that module to other modules.

Abstract translation: 可编程逻辑器件集成电路（“PLD”）上的收发器电路优选地设置在多个相同或至少相似的模块中。 每个模块优选地包括多个收发器通道和时钟源单元。 提供时钟分配电路用于将模块的时钟源的信号分配给该模块中的所有收发器通道，并且还选择性地超出该模块到其他模块。

公开(公告)号：US07759972B1

公开(公告)日：2010-07-20

申请号：US11981934

申请日：2007-10-31

Applicant: Sergey Shumarayev ,  Wilson Wong ,  Weiqi Ding ,  Thungoc M. Tran ,  Tim Tri Hoang

Inventor： Sergey Shumarayev ,  Wilson Wong ,  Weiqi Ding ,  Thungoc M. Tran ,  Tim Tri Hoang

IPC: H01L25/00

CPC classification number: H03K19/177

Abstract: An integrated circuit device such as a programmable logic device (“PLD”) includes a plurality of blocks of legacy circuitry. These legacy blocks leave at least one corner of the device unoccupied by such legacy circuitry. This at least one corner is used for relatively newly developed circuitry so as to simplify and speed the design of relatively new circuitry, to avoid having to significantly redesign any of the legacy circuitry to give the device the capabilities of the new circuitry, etc. The relatively newly developed circuitry may be high-speed serial data signal interface (“HSSI”) circuitry that is capable of operating at serial data rates faster than any legacy HSSI circuitry on the device.

Abstract translation: 诸如可编程逻辑器件（“PLD”）的集成电路器件包括多个遗留电路块。 这些传统块离开设备的至少一个角落，不被这种遗留电路占用。 这个至少一个角用于相对新开发的电路，以便简化和加速相对新的电路的设计，以避免必须重新设计任何传统电路以给予设备新电路的能力等。 相对新开发的电路可以是高速串行数据信号接口（“HSSI”）电路，其能够以比设备上的任何传统HSSI电路更快的串行数据速率工作。

公开(公告)号：US07602255B1

公开(公告)日：2009-10-13

申请号：US11861144

申请日：2007-09-25

Applicant: Kang-Wei Lai ,  Ninh D. Ngo ,  Kazi Asaduzzaman ,  Mian Z. Smith ,  Wanli Chang ,  Tim Tri Hoang

Inventor： Kang-Wei Lai ,  Ninh D. Ngo ,  Kazi Asaduzzaman ,  Mian Z. Smith ,  Wanli Chang ,  Tim Tri Hoang

IPC: H03L7/00

CPC classification number: H03L7/0895 ,  H03L7/0812

Abstract: A feedback loop, such as a phase-locked loop, on an integrated circuit has a detector, a charge pump, and a loop filter. The charge pump adjusts its output current in response to variations in a process of the integrated circuit to reduce variations in the loop bandwidth. The charge pump also adjusts its output current in response to variations in a resistance of a resistor in the loop filter to reduce variations in the loop bandwidth. The charge pump can also adjust its output current in response to variations in a temperature of the integrated circuit to reduce variations in the loop bandwidth. A delay-locked loop on an integrated circuit has a phase detector and a charge pump. The charge pump adjusts its output current in response to variations in the temperature and the process of the integrated circuit to reduce changes in the loop bandwidth.

Abstract translation: 在集成电路上的反馈回路（例如锁相环）具有检测器，电荷泵和环路滤波器。 电荷泵响应于集成电路的过程中的变化来调节其输出电流，以减少环路带宽的变化。 电荷泵还响应于环路滤波器中的电阻器的电阻的变化来调整其输出电流，以减少环路带宽的变化。 电荷泵还可以响应于集成电路的温度变化来调节其输出电流，以减少环路带宽的变化。 集成电路上的延迟锁定环路具有相位检测器和电荷泵。 电荷泵响应于集成电路的温度和过程的变化来调整其输出电流，以减少环路带宽的变化。

公开(公告)号：US07576570B1

公开(公告)日：2009-08-18

申请号：US11508607

申请日：2006-08-22

Applicant: Wilson Wong ,  Sergey Shumarayev ,  Simardeep Maangat ,  Thungoc M. Tran ,  Tim Tri Hoang

Inventor： Wilson Wong ,  Sergey Shumarayev ,  Simardeep Maangat ,  Thungoc M. Tran ,  Tim Tri Hoang

IPC: H03K5/153

CPC classification number: H03K5/153 ,  H03K5/24

Abstract: Precision amplitude detection circuitry without pattern dependencies is provided that includes rectifier circuitry to output a rectified voltage signal and delay circuitry to send one or more delayed or phase-shifted versions of a differential signal input to the rectifier circuitry. The delayed versions of the differential signal input may be delayed in order to reduce or eliminate the dips in the input seen by the rectifier. This may help correct for low rectified voltage levels. The signal amplitude detection circuitry of the present invention may be incorporated on the input pin of any programmable logic resource and may be included in communication circuitry of a PLD. The precision amplitude detection circuitry may operate in the Gbps (gigabit per second) range.

Abstract translation: 提供了没有图形相关性的精密幅度检测电路，其包括整流电路，用于输出整流电压信号和延迟电路，以将一个或多个差分信号输入的延迟或相移版本发送到整流器电路。 可以延迟差分信号输入的延迟版本，以便减少或消除由整流器看到的输入中的下降。 这可能有助于校正低整流电压电平。 本发明的信号幅度检测电路可以结合在任何可编程逻辑资源的输入引脚上，并且可以被包括在PLD的通信电路中。 精度幅度检测电路可以以Gbps（千兆位/秒）范围工作。

公开(公告)号：US20090161738A1

公开(公告)日：2009-06-25

申请号：US12283652

申请日：2008-09-15

Applicant: Neville Carvalho ,  Allan Thomas Davidson ,  Andy Turudic ,  Bruce B. Pedersen ,  David W. Mendel ,  Kalyan Kankipati ,  Michael Menghui Zheng ,  Sergey Shumarayev ,  Seungmyon Park ,  Tim Tri Hoang ,  Kumara Tharmalingam

Inventor： Neville Carvalho ,  Allan Thomas Davidson ,  Andy Turudic ,  Bruce B. Pedersen ,  David W. Mendel ,  Kalyan Kankipati ,  Michael Menghui Zheng ,  Sergey Shumarayev ,  Seungmyon Park ,  Tim Tri Hoang ,  Kumara Tharmalingam

IPC: H04L7/00 ,  H04B1/38

CPC classification number: H04L25/14

Abstract: A transceiver system with reduced latency uncertainty is described. In one implementation, the transceiver system has a word aligner latency uncertainty of zero. In another implementation, the transceiver system has a receiver-to-transmitter transfer latency uncertainty of zero. In yet another implementation, the transceiver system has a word aligner latency uncertainty of zero and a receiver-to-transmitter transfer latency uncertainty of zero. In one specific implementation, the receiver-to-transmitter transfer latency uncertainty is eliminated by using the transmitter parallel clock as a feedback signal in the transmitter phase locked loop (PLL). In one implementation, this is achieved by optionally making the transmitter divider, which generates the transmitter parallel clock, part of the feedback path of the transmitter PLL. In one implementation, the word aligner latency uncertainty is eliminated by using a bit slipper to slip bits in such a way so that the total delay due to the word alignment and bit slipping is constant for all phases of the recovered clock. This allows for having a fixed and known latency between the receipt and transmission of bits for all phases of parallelization by the deserializer. In one specific implementation, the total delay due to the bit shifting by the word aligner and the bit slipping by the bit slipper is zero since the bit slipper slips bits so as to compensate for the bit shifting that was performed by the word aligner.

Abstract translation: 描述了具有降低的等待时间不确定性的收发机系统。 在一个实现中，收发器系统具有字对齐器等待时间不确定度为零。 在另一个实现中，收发器系统具有接收器到发射器的传输等待时间不确定度为零。 在另一个实现中，收发器系统具有字对齐器延迟不确定度为零和接收器到发射器的传输等待时间不确定度为零。 在一个具体实现中，通过在发射机锁相环（PLL）中使用发射机并行时钟作为反馈信号来消除接收机到发射机的传输等待时间不确定性。 在一个实现中，这通过可选地使发射机分频器（其产生发射机并行时钟）作为发射机PLL的反馈路径的一部分来实现。 在一个实施方案中，通过使用位拖动器以这样的方式滑动位来消除字对齐器延迟不确定性，使得由于字对齐和位滑动引起的总延迟对于恢复时钟的所有阶段是恒定的。 这允许在由解串器的并行化的所有阶段的位的接收和传输之间具有固定和已知的等待时间。 在一个具体实现中，由于位对准器的位移和由位拖动器的位滑动导致的总延迟为零，因为位拖动器滑动位，以补偿由字对准器执行的位移。