公开(公告)号：US07749835B2

公开(公告)日：2010-07-06

申请号：US12048263

申请日：2008-03-14

申请人： Xi Li ,  Kangguo Cheng ,  Johnathan Faltermeier

发明人： Xi Li ,  Kangguo Cheng ,  Johnathan Faltermeier

IPC分类号： H01L21/84 ,  H01L21/8242

CPC分类号： H01L29/945 ,  H01L21/32137 ,  H01L21/76232 ,  H01L21/84 ,  H01L27/1087 ,  H01L29/66181

摘要： A semiconductor structure is described. The structure includes a trench opening formed in a semiconductor substrate having a semiconductor-on-insulator (SOI) layer and a buried insulating (BOX) layer; and a filling material formed in the trench opening, the filling material forming a “V” shape within the trench memory cell, wherein the “V” shape includes a top portion substantially adjacent to a top surface of the BOX layer. A method of fabricating the semiconductor structure is also described. The method includes forming a trench opening in a semiconductor substrate having an SOI layer and a BOX layer; laterally etching the BOX layer such that a portion of the trench opening associated with the BOX layer is substantially greater than a portion of the trench opening associated with the SOI layer; filling the trench opening with a filling material; and recessing the filling material.

摘要翻译： 描述半导体结构。 该结构包括形成在具有绝缘体上半导体（SOI）层和掩埋绝缘（BOX）层的半导体衬底中的沟槽开口; 以及形成在所述沟槽开口中的填充材料，所述填充材料在所述沟槽存储单元内形成“V”形，其中所述“V”形包括基本上邻近所述BOX层的顶表面的顶部。 还描述了制造半导体结构的方法。 该方法包括在具有SOI层和BOX层的半导体衬底中形成沟槽开口; 横向蚀刻BOX层，使得与BOX层相关联的沟槽开口的一部分基本上大于与SOI层相关联的沟槽开口的一部分; 用填充材料填充沟槽开口; 并使填充材料凹陷。

公开(公告)号：US20100038751A1

公开(公告)日：2010-02-18

申请号：US12191430

申请日：2008-08-14

申请人： HUILONG ZHU ,  Babar A. Khan ,  Xi Li ,  Joyce C. Liu ,  Thomas A. Wallner

发明人： HUILONG ZHU ,  Babar A. Khan ,  Xi Li ,  Joyce C. Liu ,  Thomas A. Wallner

IPC分类号： H01L29/00 ,  H01L21/20

CPC分类号： H01L29/66181 ,  H01L27/10861

摘要： A deep trench (DT) capacitor comprises a trench in a silicon layer, a buried plate surrounding the trench, a dielectric layer lining the trench, and a node conductor in the trench. The top surface of the poly node is higher than the surface of the silicon layer, so that it is high enough to ensure that a nitride liner used as a CMP etch stop for STI oxide surrounding a top portion of the poly node will be higher than the STI oxide, so that the nitride liner can be removed prior to forming a silicide contact on top of the poly node.

摘要翻译： 深沟槽（DT）电容器包括硅层中的沟槽，围绕沟槽的掩埋板，衬套沟槽的电介质层和沟槽中的节点导体。 多晶硅节点的顶表面高于硅层的表面，使得其足够高以确保用作CMP蚀刻的氮化物衬垫停止用于围绕多晶硅节点的顶部的STI氧化物将高于 STI氧化物，使得氮化物衬垫可以在在多晶硅节点的顶部形成硅化物接触之前被去除。

公开(公告)号：US20090210784A1

公开(公告)日：2009-08-20

申请号：US12031401

申请日：2008-02-14

申请人： Blake Sullivan ,  Tal Broda ,  Edward J. Farrell ,  Xi Li ,  Congxiao Lu ,  Shailesh Vinayaka ,  Dipankar Bajpai ,  Max Starets ,  David Allen Schneider

发明人： Blake Sullivan ,  Tal Broda ,  Edward J. Farrell ,  Xi Li ,  Congxiao Lu ,  Shailesh Vinayaka ,  Dipankar Bajpai ,  Max Starets ,  David Allen Schneider

IPC分类号： G06F17/00

CPC分类号： G06F17/30867

摘要： A system that pushes active data to a client receives a first request for a page that includes active data from the client. The active data includes a component and a corresponding model for a data source of the component. The system determines if the model is active and if so, instantiates an encoder that corresponds to the component. The system queries the model for the active data and renders a user interface representation of the data. The system then returns a response to the request with the user interface representation.

摘要翻译： 将活动数据推送到客户端的系统接收到包含来自客户端的活动数据的页面的第一请求。 活动数据包括组件和组件的数据源的对应模型。 系统确定模型是否处于活动状态，如果是，则实例化与组件对应的编码器。 系统查询模型中的活动数据，并呈现数据的用户界面表示。 系统然后使用用户界面表示返回对请求的响应。

公开(公告)号：US07560387B2

公开(公告)日：2009-07-14

申请号：US11275707

申请日：2006-01-25

申请人： Scott D. Allen ,  Kangguo Cheng ,  Xi Li ,  Kevin R. Winstel

发明人： Scott D. Allen ,  Kangguo Cheng ,  Xi Li ,  Kevin R. Winstel

IPC分类号： H01L21/311

CPC分类号： H01L21/3081 ,  H01L21/31116

摘要： Methods for opening a hard mask and a silicon-on-insulator substrate in a single process chamber are disclosed. In one embodiment, the method includes patterning a photoresist over a stack including an anti-reflective coating (ARC) layer, a silicon dioxide (SiO2) based hard mask layer, a silicon nitride pad layer, a silicon dioxide (SiO2) pad layer and the SOI substrate, wherein the SOI substrate includes a silicon-on-insulator layer and a buried silicon dioxide (SiO2) layer; and in a single process chamber: opening the ARC layer; etching the silicon dioxide (SiO2) based hard mask layer; etching the silicon nitride pad layer; etching the silicon dioxide (SiO2) pad layer; and etching the SOI substrate. Etching all layers in a single chamber reduces the turn-around-time, lowers the process cost, facilitates process control and/or improve a trench profile.

摘要翻译： 公开了在单个处理室中打开硬掩模和绝缘体上硅衬底的方法。 在一个实施例中，该方法包括在包括抗反射涂层（ARC）层，基于二氧化硅（SiO 2）的硬掩模层，氮化硅衬垫层，二氧化硅（SiO 2）衬垫层和叠层 SOI衬底，其中所述SOI衬底包括绝缘体上硅层和掩埋二氧化硅（SiO 2）层; 并在单个处理室中：打开ARC层; 蚀刻基于二氧化硅（SiO 2）的硬掩模层; 蚀刻氮化硅焊盘层; 蚀刻二氧化硅（SiO 2）垫层; 并蚀刻SOI衬底。 在单个室中蚀刻所有层减少了周转时间，降低了工艺成本，便于工艺控制和/或改善沟槽轮廓。

公开(公告)号：US20090108306A1

公开(公告)日：2009-04-30

申请号：US11931112

申请日：2007-10-31

申请人： Kangguo Cheng ,  Johnathan E. Faltermeier ,  Xi Li

发明人： Kangguo Cheng ,  Johnathan E. Faltermeier ,  Xi Li

IPC分类号： H01L29/94 ,  H01L21/311

CPC分类号： H01L21/32137 ,  H01L21/32115 ,  H01L29/66181

摘要： Columnar elements which extend to varying heights above a major surface of a substrate, e.g., polysilicon studs within trenches in the substrate, are recessed to a uniform depth below the major surface. The columnar elements are etched selectively with respect to a material exposed at the surface in an at least partly lateral direction so that the columnar elements are recessed to a uniform depth below the major surface at walls of the trenches.

摘要翻译： 在衬底的主表面上方延伸到不同高度的柱状元件（例如衬底中的沟槽内的多晶硅柱）凹陷到主表面下方的均匀深度。 相对于在表面上以至少部分横向方向暴露的材料选择性地蚀刻柱状元件，使得柱状元件在沟槽的壁处凹陷到主表面下方的均匀深度。

公开(公告)号：US07494891B2

公开(公告)日：2009-02-24

申请号：US11533928

申请日：2006-09-21

申请人： Kangguo Cheng ,  Johnathan E. Faltermeier ,  Xi Li

发明人： Kangguo Cheng ,  Johnathan E. Faltermeier ,  Xi Li

IPC分类号： H01L21/20

CPC分类号： H01L29/945 ,  H01L29/66181

摘要： A method forms a node dielectric in a bottle shaped trench and then deposits an initial conductor within the lower portion of the bottle shaped trench, such that a void is formed within the initial conductor. Next, the method forms an insulating collar in the upper portion of the bottle shaped trench above the initial conductor. Then, the method simultaneously etches a center portion of the insulating collar and the initial conductor until the void is exposed. This etching process forms a center opening within the insulating collar and the initial conductor. Additional conductor is deposited in the center opening such that the additional conductor is formed at least to the level of the surface of the substrate.

摘要翻译： 一种方法在瓶形沟槽中形成节点电介质，然后将初始导体沉积在瓶形沟槽的下部，使得在初始导体内形成空隙。 接下来，该方法在初始导体上方的瓶形沟槽的上部形成绝缘套环。 然后，该方法同时蚀刻绝缘套环的中心部分和初始导体，直到暴露出空隙。 该蚀刻工艺在绝缘环和初始导体内形成中心开口。 附加导体沉积在中心开口中，使得附加导体至少形成至基底表面的水平。

公开(公告)号：US20080248625A1

公开(公告)日：2008-10-09

申请号：US12120535

申请日：2008-05-14

申请人： Kangguo Cheng ,  David M. Dobuzinsky ,  Xi Li

发明人： Kangguo Cheng ,  David M. Dobuzinsky ,  Xi Li

IPC分类号： H01L21/441

CPC分类号： H01L29/945 ,  H01L28/84 ,  H01L29/66181

摘要： Methods for enhancing trench capacitance and a trench capacitor so formed are disclosed. In one embodiment a method includes forming a first portion of a trench; depositing a dielectric layer in the first portion; performing a reactive ion etching including a first stage to etch the dielectric layer and form a micro-mask on a bottom surface of the first portion of the trench and a second stage to form a second portion of the trench having a rough sidewall; depositing a node dielectric; and filling the trench with a conductor. The rough sidewall enhances trench capacitance without increasing processing complexity or cost.

公开(公告)号：US20080246068A1

公开(公告)日：2008-10-09

申请号：US12138536

申请日：2008-06-13

申请人： Kangguo Cheng ,  Xi Li

发明人： Kangguo Cheng ,  Xi Li

IPC分类号： H01L29/94

CPC分类号： H01L29/66181 ,  H01L27/10829 ,  H01L27/1087

摘要： A trench structure, a method of forming the trench structure, a memory cell using the trench structure and a method of forming a memory cell using the trench structure. The trench structure includes: a substrate; a trench having contiguous upper, middle and lower regions, the trench extending from a top surface of said substrate into said substrate; the upper region of the trench having a vertical sidewall profile; and the middle region of the trench having a tapered sidewall profile.

摘要翻译： 沟槽结构，形成沟槽结构的方法，使用沟槽结构的存储单元以及使用沟槽结构形成存储单元的方法。 沟槽结构包括：衬底; 具有连续的上，中和下区域的沟槽，所述沟槽从所述衬底的顶表面延伸到所述衬底中; 所述沟槽的上部区域具有垂直侧壁轮廓; 并且沟槽的中间区域具有锥形侧壁轮廓。

公开(公告)号：US20070250548A1

公开(公告)日：2007-10-25

申请号：US11408454

申请日：2006-04-21

申请人： Ziling Huo ,  Xi Li ,  Phaisit Chewputtanagul

发明人： Ziling Huo ,  Xi Li ,  Phaisit Chewputtanagul

IPC分类号： G06F17/30

CPC分类号： G06T7/0012 ,  G06K9/00147 ,  G06K9/6284 ,  G06T2207/30024

摘要： In accordance with the principles of the invention, methods, systems, and computer-readable mediums are provided for processing image data representing cellular analysis result data including accessing image data; generating an intensity histogram based on the image data; transforming the intensity histogram into a stepped image; performing normalized cross-correlation between the stepped image and a reference image to measure similarity; and determining an abnormality based on the measured similarity.

摘要翻译： 根据本发明的原理，提供方法，系统和计算机可读介质，用于处理表示包括访问图像数据的蜂窝分析结果数据的图像数据; 基于图像数据生成强度直方图; 将强度直方图变换为阶梯图像; 执行阶梯图像和参考图像之间的归一化互相关以测量相似度; 以及基于所测量的相似度来确定异常。

公开(公告)号：US20070172965A1

公开(公告)日：2007-07-26

申请号：US11275663

申请日：2006-01-23

申请人： Kangguo Cheng ,  Xi Li

发明人： Kangguo Cheng ,  Xi Li

IPC分类号： H01L21/66 ,  H01L21/76

CPC分类号： H01L21/76224 ,  H01L22/12

摘要： Methods of determining trench volume are disclosed. In one embodiment, the method includes providing a semiconductor substrate with at least one trench in a trench area; filling each trench with a filling material; measuring a step height between the trench area and a trench free area; and determining the trench volume based on the step height. The embodiments provide a simple, nondestructive, cost-effective, highly scalable and reliable trench volume measurement. The step height can also be used as part of a method to project trench capacitance where the trench will be used for a trench capacitor.

摘要翻译： 公开了确定沟槽体积的方法。 在一个实施例中，该方法包括在沟槽区域中提供具有至少一个沟槽的半导体衬底; 用填充材料填充每个沟槽; 测量沟槽区域和无沟槽区域之间的台阶高度; 以及基于所述台阶高度确定所述沟槽体积。 这些实施例提供了简单的，非破坏性的，成本有效的，高度可扩展的和可靠的沟槽体积测量。 步长也可用作投影沟槽电容的方法的一部分，其中沟槽将用于沟槽电容器。