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公开(公告)号：US07858485B2
公开(公告)日：2010-12-28
申请号：US12191430
申请日：2008-08-14
申请人： Huilong Zhu , Babar A. Khan , Xi Li , Joyce C. Liu , Thomas A. Wallner
发明人： Huilong Zhu , Babar A. Khan , Xi Li , Joyce C. Liu , Thomas A. Wallner
IPC分类号： H01L21/20
CPC分类号： H01L29/66181 , H01L27/10861
摘要： A deep trench (DT) capacitor comprises a trench in a silicon layer, a buried plate surrounding the trench, a dielectric layer lining the trench, and a node conductor in the trench. The top surface of the poly node is higher than the surface of the silicon layer, so that it is high enough to ensure that a nitride liner used as a CMP etch stop for STI oxide surrounding a top portion of the poly node will be higher than the STI oxide, so that the nitride liner can be removed prior to forming a silicide contact on top of the poly node.
摘要翻译： 深沟槽（DT）电容器包括硅层中的沟槽，围绕沟槽的掩埋板，衬套沟槽的电介质层和沟槽中的节点导体。 多晶硅节点的顶表面高于硅层的表面，使得其足够高以确保用作CMP蚀刻的氮化物衬垫停止用于围绕多晶硅节点的顶部的STI氧化物将高于 STI氧化物，使得氮化物衬垫可以在在多晶硅节点的顶部形成硅化物接触之前被去除。
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公开(公告)号：US20100038751A1
公开(公告)日：2010-02-18
申请号：US12191430
申请日：2008-08-14
申请人： HUILONG ZHU , Babar A. Khan , Xi Li , Joyce C. Liu , Thomas A. Wallner
发明人： HUILONG ZHU , Babar A. Khan , Xi Li , Joyce C. Liu , Thomas A. Wallner
CPC分类号： H01L29/66181 , H01L27/10861
摘要： A deep trench (DT) capacitor comprises a trench in a silicon layer, a buried plate surrounding the trench, a dielectric layer lining the trench, and a node conductor in the trench. The top surface of the poly node is higher than the surface of the silicon layer, so that it is high enough to ensure that a nitride liner used as a CMP etch stop for STI oxide surrounding a top portion of the poly node will be higher than the STI oxide, so that the nitride liner can be removed prior to forming a silicide contact on top of the poly node.
摘要翻译： 深沟槽（DT）电容器包括硅层中的沟槽，围绕沟槽的掩埋板，衬套沟槽的电介质层和沟槽中的节点导体。 多晶硅节点的顶表面高于硅层的表面，使得其足够高以确保用作CMP蚀刻的氮化物衬垫停止用于围绕多晶硅节点的顶部的STI氧化物将高于 STI氧化物，使得氮化物衬垫可以在在多晶硅节点的顶部形成硅化物接触之前被去除。
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公开(公告)号：US20130256748A1
公开(公告)日：2013-10-03
申请号：US13431414
申请日：2012-03-27
申请人： William F. Clark, JR. , Robert J. Gauthier, JR. , Terence B. Hook , Junjun Li , Theodorus E. Standaert , Thomas A. Wallner
发明人： William F. Clark, JR. , Robert J. Gauthier, JR. , Terence B. Hook , Junjun Li , Theodorus E. Standaert , Thomas A. Wallner
IPC分类号： H01L29/73 , G06F17/50 , H01L21/331
CPC分类号： H01L27/1211 , H01L21/7624 , H01L21/823821 , H01L21/845 , H01L27/0207 , H01L27/0262 , H01L27/0924 , H01L27/1203 , H01L29/66795 , H01L29/785
摘要： Device structures, design structures, and fabrication methods for passive devices that may be used as electrostatic discharge protection devices in fin-type field-effect transistor integrated circuit technologies. A device region is formed in a trench and is coupled with a handle wafer of a semiconductor-on-insulator substrate. The device region extends through a buried insulator layer of the semiconductor-on-insulator substrate toward a top surface of a device layer of the semiconductor-on-insulator substrate. The device region is comprised of lightly-doped semiconductor material. The device structure further includes a doped region formed in the device region and that defines a junction. A portion of the device region is laterally positioned between the doped region and the buried insulator layer of the semiconductor-on-insulator substrate. Another region of the device layer may be patterned to form fins for fin-type field-effect transistors.
摘要翻译： 无源器件的器件结构，设计结构和制造方法可用作鳍式场效应晶体管集成电路技术中的静电放电保护器件。 器件区域形成在沟槽中并且与绝缘体上半导体衬底的处理晶片耦合。 器件区域延伸穿过绝缘体上半导体衬底的掩埋绝缘体层朝向绝缘体上半导体衬底的器件层的顶表面。 器件区域由轻掺杂的半导体材料组成。 器件结构还包括形成在器件区域中并限定结的掺杂区域。 器件区域的一部分横向地位于绝缘体上半导体衬底的掺杂区域和掩埋绝缘体层之间。 可以对器件层的另一区域进行构图以形成翅片型场效应晶体管的鳍片。
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公开(公告)号：US20110159655A1
公开(公告)日：2011-06-30
申请号：US13045679
申请日：2011-03-11
IPC分类号： H01L21/336
CPC分类号： H01L29/7848 , H01L21/26513 , H01L29/165 , H01L29/66628 , H01L29/66636 , H01L29/78
摘要： Stress enhanced transistor devices and methods of fabricating the same are provided. In one embodiment, a transistor device comprises: a gate conductor disposed above a semiconductor substrate between a pair of dielectric spacers, wherein the semiconductor substrate comprises a channel region underneath the gate conductor and recessed regions on opposite sides of the channel region, wherein the recessed regions undercut the dielectric spacers to form undercut areas of the channel region; and epitaxial source and drain regions disposed in the recessed regions of the semiconductor substrate and extending laterally underneath the dielectric spacers into the undercut areas of the channel region.
摘要翻译： 提供了应力增强型晶体管器件及其制造方法。 在一个实施例中，晶体管器件包括：栅极导体，设置在一对电介质间隔物之间的半导体衬底之上，其中半导体衬底包括位于栅极导体下方的沟道区域和沟道区域相对侧上的凹陷区域， 区域覆盖电介质间隔物以形成通道区域的底切区域; 以及设置在半导体衬底的凹陷区域中的外延源极和漏极区域，并且在电介质间隔物的下方横向延伸到沟道区域的底切区域中。
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公开(公告)号：US20110057266A1
公开(公告)日：2011-03-10
申请号：US12556205
申请日：2009-09-09
IPC分类号： H01L21/8249 , H01L27/06
CPC分类号： H01L21/8249 , H01L27/0623
摘要： A high-k gate dielectric layer and a metal gate layer are formed and patterned to expose semiconductor surfaces in a bipolar junction transistor region, while covering a CMOS region. A disposable material portion is formed on a portion of the exposed semiconductor surfaces in the bipolar junction transistor area. A semiconductor layer and a dielectric layer are deposited and patterned to form gate stacks including a semiconductor portion and a dielectric gate cap in the CMOS region and a cavity containing mesa over the disposable material portion in the bipolar junction transistor region. The disposable material portion is selectively removed and a base layer including an epitaxial portion and a polycrystalline portion fills the cavity formed by removal of the disposable material portion. The emitter formed by selective epitaxy fills the cavity in the mesa.
摘要翻译： 形成高k栅极电介质层和金属栅极层，并图案化以暴露双极结型晶体管区域中的半导体表面，同时覆盖CMOS区域。 一次性材料部分形成在双极结型晶体管区域中暴露的半导体表面的一部分上。 沉积半导体层和电介质层，以形成包括CMOS区域中的半导体部分和介电栅极盖的栅极堆叠，以及在双极结型晶体管区域中的一次性材料部分上的包含台面的空腔。 选择性地去除一次性材料部分，并且包括外延部分和多晶部分的基层填充通过去除一次性材料部分而形成的空腔。 通过选择性外延形成的发射体填充台面中的空腔。
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公开(公告)号：US08787074B2
公开(公告)日：2014-07-22
申请号：US13273271
申请日：2011-10-14
CPC分类号： G11C29/50008 , G11C11/41 , G11C2029/0403 , G11C2029/5002 , H01L22/34
摘要： A static random access memory (SRAM) test structure includes a p-type source/drain implant region comprising contacts (CAs), wherein the CAs in the p-type source/drain implant region comprise a first plurality of bit line, ground, and node CAs, and wherein the CAs in the p-type source/drain implant region are grounded during an inspection of the SRAM test structure; and an ungrounded region, the ungrounded region being distinct from the p-type source/drain implant region and being ungrounded during the inspection of the SRAM test structure, the ungrounded region comprising contacts (CAs) and rectangular contacts (CArecs) comprising a second plurality of bit line, ground, and node CAs, and further comprising a first plurality of Vdd CAs and rectangular contacts (CArecs), and wherein a CA or CArec in the ungrounded region is grounded during the inspection in the event of a short to a CA in the p-type source/drain implant region.
摘要翻译： 静态随机存取存储器（SRAM）测试结构包括包括触点（CA）的p型源极/漏极注入区域，其中p型源极/漏极注入区域中的CA包括第一多个位线，接地和 节点CA，并且其中在检测SRAM测试结构期间，p型源极/漏极注入区域中的CA接地; 和未接地区域，所述未接地区域与所述p型源极/漏极注入区域不同，并且在所述SRAM测试结构的检查期间不接地，所述未接地区域包括接触（CA）和矩形触点（CArecs），所述接触区域包括第二多个 位线，接地和节点CA，并且还包括第一多个Vdd CA和矩形触点（CArecs），并且其中在短路到CA的情况下，在未接地区域中的CA或CArec在检查期间接地 在p型源极/漏极注入区域中。
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公开(公告)号：US20130094315A1
公开(公告)日：2013-04-18
申请号：US13273271
申请日：2011-10-14
IPC分类号： G11C29/00
CPC分类号： G11C29/50008 , G11C11/41 , G11C2029/0403 , G11C2029/5002 , H01L22/34
摘要： A static random access memory (SRAM) test structure includes a p-type source/drain implant region comprising contacts (CAs), wherein the CAs in the p-type source/drain implant region comprise a first plurality of bit line, ground, and node CAs, and wherein the CAs in the p-type source/drain implant region are grounded during an inspection of the SRAM test structure; and an ungrounded region, the ungrounded region being distinct from the p-type source/drain implant region and being ungrounded during the inspection of the SRAM test structure, the ungrounded region comprising contacts (CAs) and rectangular contacts (CArecs) comprising a second plurality of bit line, ground, and node CAs, and further comprising a first plurality of Vdd CAs and rectangular contacts (CArecs), and wherein a CA or CArec in the ungrounded region is grounded during the inspection in the event of a short to a CA in the p-type source/drain implant region.
摘要翻译： 静态随机存取存储器（SRAM）测试结构包括包括触点（CA）的p型源极/漏极注入区域，其中p型源极/漏极注入区域中的CA包括第一多个位线，接地和 节点CA，并且其中在检测SRAM测试结构期间，p型源极/漏极注入区域中的CA接地; 和未接地区域，所述未接地区域与所述p型源极/漏极注入区域不同，并且在所述SRAM测试结构的检查期间不接地，所述未接地区域包括接触（CA）和矩形触点（CArecs），所述接触区域包括第二多个 位线，接地和节点CA，并且还包括第一多个Vdd CA和矩形触点（CArecs），并且其中在短路到CA的情况下，在未接地区域中的CA或CArec在检查期间接地 在p型源极/漏极注入区域中。
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8.发明授权Method of forming bipolar transistor integrated with metal gate CMOS devices 失效与金属栅极CMOS器件集成的双极晶体管的形成方法公开(公告)号：US08129234B2
公开(公告)日：2012-03-06
申请号：US12556205
申请日：2009-09-09
IPC分类号： H01L21/8249
CPC分类号： H01L21/8249 , H01L27/0623
摘要： A high-k gate dielectric layer and a metal gate layer are formed and patterned to expose semiconductor surfaces in a bipolar junction transistor region, while covering a CMOS region. A disposable material portion is formed on a portion of the exposed semiconductor surfaces in the bipolar junction transistor area. A semiconductor layer and a dielectric layer are deposited and patterned to form gate stacks including a semiconductor portion and a dielectric gate cap in the CMOS region and a cavity containing mesa over the disposable material portion in the bipolar junction transistor region. The disposable material portion is selectively removed and a base layer including an epitaxial portion and a polycrystalline portion fills the cavity formed by removal of the disposable material portion. The emitter formed by selective epitaxy fills the cavity in the mesa.
摘要翻译： 形成高k栅极电介质层和金属栅极层，并图案化以暴露双极结型晶体管区域中的半导体表面，同时覆盖CMOS区域。 一次性材料部分形成在双极结型晶体管区域中暴露的半导体表面的一部分上。 沉积半导体层和电介质层，以形成包括CMOS区域中的半导体部分和介电栅极盖的栅极堆叠，以及在双极结型晶体管区域中的一次性材料部分上的包含台面的空腔。 选择性地去除一次性材料部分，并且包括外延部分和多晶部分的基层填充通过去除一次性材料部分而形成的空腔。 通过选择性外延形成的发射体填充台面中的空腔。
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9.发明授权Monocrystalline extrinsic base and emitter heterojunction bipolar transistor and related methods 有权单晶外基极和发射极异质结双极晶体管及相关方法公开(公告)号：US07521772B2
公开(公告)日：2009-04-21
申请号：US11557692
申请日：2006-11-08
申请人： Thomas N Adam , Thomas A. Wallner
发明人： Thomas N Adam , Thomas A. Wallner
IPC分类号： H01L29/00
CPC分类号： H01L29/7378 , H01L29/0821 , H01L29/66242
摘要： A heterostructure bipolar transistor (HBT) and related methods are disclosed. In one embodiment, the HBT includes a heterostructure bipolar transistor (HBT) including: a substrate; a monocrystalline emitter atop the substrate; a collector in the substrate; at least one isolation region adjacent to the collector; a monocrystalline silicon germanium (SiGe) intrinsic base extending over each isolation region; and a monocrystalline silicon extrinsic base. A method may include forming the intrinsic and extrinsic base and the emitter as monocrystalline, with the extrinsic base (and emitter) formed in a self-aligned fashion utilizing selective-epitaxial growth on porous silicon. As a result, some mask levels can be omitted, making this an inexpensive alternative to conventional processing.
摘要翻译： 公开了异质结双极晶体管（HBT）及相关方法。 在一个实施例中，HBT包括异质结双极晶体管（HBT），包括：衬底; 衬底顶部的单晶发射体; 底物中的收集器; 与收集器相邻的至少一个隔离区域; 在每个隔离区域上延伸的单晶硅锗（SiGe）本征基极; 和单晶硅外在碱。 一种方法可以包括将本征和非本征碱和发射体形成为单晶，其中外部碱（和发射体）以自对准方式形成，利用多孔硅上的选择性外延生长。 结果，可以省略一些掩模级别，这使得它成为常规处理的便宜的替代方案。
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10.发明申请HETEROJUNCTION BIPOLAR TRANSISTOR WITH MONOCRYSTALLINE BASE AND RELATED METHODS 审中-公开具有单晶基体的异相双极晶体管及相关方法公开(公告)号：US20080121937A1
公开(公告)日：2008-05-29
申请号：US11557680
申请日：2006-11-08
申请人： Thomas N Adam , Thomas A. Wallner
发明人： Thomas N Adam , Thomas A. Wallner
IPC分类号： H01L29/737 , H01L21/331
CPC分类号： H01L29/66242 , H01L29/7378
摘要： A heterostructure bipolar transistor (HBT) and related methods are disclosed. In one embodiment, the HBT includes a substrate; a polysilicon emitter atop the substrate; a collector in the substrate; at least one isolation region adjacent to the collector; an intrinsic base including monocrystalline silicon germanium extending over each isolation region; and a monocrystalline extrinsic base. One method includes replacing isolation region formation with formation of porous implanted silicon, which is later converted to a dielectric. As a result, a monocrystalline silicon germanium profile base layer may be formed with extended lateral dimensions over the isolation region(s).
摘要翻译： 公开了异质结双极晶体管（HBT）及相关方法。 在一个实施例中，HBT包括衬底; 衬底顶部的多晶硅发射体; 底物中的收集器; 与收集器相邻的至少一个隔离区域; 包括在每个隔离区域上延伸的单晶硅锗的本征基底; 和单晶外基。 一种方法包括用形成多孔注入的硅代替隔离区形成，后者转化为电介质。 结果，可以在隔离区域上形成具有延伸的横向尺寸的单晶硅锗轮廓基底层。
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